Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...

diff --cc Documentation/devicetree/bindings/pwm/pwm-samsung.txt
index 4caa1a78863e088415ca6af4ebd756f354ab3455,39f0ca7008ba37568039c6b2904b6ebb4aa1e6f9..d61fccd40bad42a746374c29f8589891bb75621f
--- 1/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
--- 2/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
@@@ -19,9 -19,23 +19,19 @@@ Required properties
  - reg: base address and size of register area
  - interrupts: list of timer interrupts (one interrupt per timer, starting at
    timer 0)
 -- #pwm-cells: number of cells used for PWM specifier - must be 3
 -   the specifier format is as follows:
 -     - phandle to PWM controller node
 -     - index of PWM channel (from 0 to 4)
 -     - PWM signal period in nanoseconds
 -     - bitmask of optional PWM flags:
 -        0x1 - invert PWM signal
+ - clock-names: should contain all following required clock names:
+     - "timers" - PWM base clock used to generate PWM signals,
+   and any subset of following optional clock names:
+     - "pwm-tclk0" - first external PWM clock source,
+     - "pwm-tclk1" - second external PWM clock source.
+   Note that not all IP variants allow using all external clock sources.
+   Refer to SoC documentation to learn which clock source configurations
+   are available.
+ - clocks: should contain clock specifiers of all clocks, which input names
+   have been specified in clock-names property, in same order.
 +- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
 +  the cells format. The only third cell flag supported by this binding is
 +  PWM_POLARITY_INVERTED.
  
  Optional properties:
  - samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular

diff --cc arch/arm/boot/dts/exynos4.dtsi
Simple merge

diff --cc arch/arm/mach-imx/clk.h
Simple merge

diff --cc drivers/clk/samsung/clk-exynos4.c
index 4e5739773c33a25f6bf5503e9261b18a11a473d2,bf5e5e1e99d9348eee77d57a407aec93df8e1913..ad5ff50c5f281a5e1c31c498c78c5a717aa464de
--- 1/drivers/clk/samsung/clk-exynos4.c
--- 2/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@@ -860,65 -855,79 +859,79 @@@ static struct samsung_gate_clock exynos
                        E4X12_GATE_IP_ISP, 2, 0, 0),
        GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
                        E4X12_GATE_IP_ISP, 3, 0, 0),
-       GATE_A(wdt, "watchdog", "aclk100",
-                       E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
-       GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
-                       E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
-       GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
-                       E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+       GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
+       GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
+                       0, 0),
+       GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
+                       0, 0),
        GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
 -                      CLK_IGNORE_UNUSED, 0),
 +                      CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
        GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
+       GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0),
+ };
+ 
+ static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+       ALIAS(mout_core, NULL, "moutcore"),
+       ALIAS(arm_clk, NULL, "armclk"),
+       ALIAS(sclk_apll, NULL, "mout_apll"),
+ };
+ 
+ static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
+       ALIAS(sclk_mpll, NULL, "mout_mpll"),
+ };
+ 
+ static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
+       ALIAS(mout_mpll_user_c, NULL, "mout_mpll"),
  };
  
  /*

diff --cc drivers/clk/tegra/clk-tegra114.c
Simple merge

diff --cc drivers/clk/zynq/clkc.c
index 089d3e30e2216e44b20067fdaf9ded66708d0bb2,e05c9e3f1385d3f45bba676e5ae77244f4c44d50..cc40fe64f2dc681c44205151537a71222e8d4990
--- 1/drivers/clk/zynq/clkc.c
--- 2/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@@ -293,8 -294,9 +295,9 @@@ static void __init zynq_clk_setup(struc
                        swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
        }
        clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
-                       swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
-                       SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);
+                       swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
+                       CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
 -                      &gem0clk_lock);
++                      &swdtclk_lock);
  
        /* DDR clocks */
        clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@@ -366,7 -369,7 +370,8 @@@
                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
                        &gem0clk_lock);
        clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
-                       CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
 -                      CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
++                      CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++                      SLCR_GEM0_CLK_CTRL, 6, 1, 0,
                        &gem0clk_lock);
        clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
                        "gem0_emio_mux", CLK_SET_RATE_PARENT,
@@@ -389,7 -393,7 +395,8 @@@
                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
                        &gem1clk_lock);
        clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
-                       CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
 -                      CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
++                      CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++                      SLCR_GEM1_CLK_CTRL, 6, 1, 0,
                        &gem1clk_lock);
        clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
                        "gem1_emio_mux", CLK_SET_RATE_PARENT,

diff --cc drivers/clocksource/samsung_pwm_timer.c
Simple merge