#include "bnx2_fw.h"
 
 #define DRV_MODULE_NAME                "bnx2"
-#define DRV_MODULE_VERSION     "2.0.18"
-#define DRV_MODULE_RELDATE     "Oct 7, 2010"
+#define DRV_MODULE_VERSION     "2.0.20"
+#define DRV_MODULE_RELDATE     "Nov 24, 2010"
 #define FW_MIPS_FILE_06                "bnx2/bnx2-mips-06-6.0.15.fw"
 #define FW_RV2P_FILE_06                "bnx2/bnx2-rv2p-06-6.0.15.fw"
 #define FW_MIPS_FILE_09                "bnx2/bnx2-mips-09-6.0.17.fw"
                val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
                      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
 
-               pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
+               REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
 
        } else {
                val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
                goto err_out_release;
        }
 
+       bnx2_set_power_state(bp, PCI_D0);
+
        /* Configure byte swap and enable write to the reg_window registers.
         * Rely on CPU to do target byte swapping on big endian systems
         * The chip's target access swapping will not swap all accesses
         */
-       pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
-                              BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
-                              BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
-
-       bnx2_set_power_state(bp, PCI_D0);
+       REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
+                  BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+                  BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
 
        bp->chip_id = REG_RD(bp, BNX2_MISC_ID);