drm/amd/display: set dram speed for all states

[WHY?]
If higher states have memory speed set to 0 MT/s currently they do not get set
to the highest value which can cause validation failures.

[HOW?]
Set unpopulated higher states to max value.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 7772beadd00067843cc22349f122f4bd41a759ae..3f93b1f2d872b3aad6deaed746acfb57f2d4fe64 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -3549,7 +3549,6 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
                        dcn3_2_soc.clock_limits[i].state = i;
                        dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
                        dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
-                       dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
 
                        /* Fill all states with max values of all these clocks */
                        dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
@@ -3568,6 +3567,11 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
                        else
                                dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 
+                       if (!dram_speed_mts[i] && i > 0)
+                               dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
+                       else
+                               dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
                        /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
                        /* PHYCLK_D18, PHYCLK_D32 */
                        dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 0b420466b6dd7cf937ff78005957bd92cd7d85d6..27d3aa7d751f2eabfca45e63ad26911f55850385 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1899,7 +1899,6 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
                        dcn3_21_soc.clock_limits[i].state = i;
                        dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
                        dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
-                       dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
 
                        /* Fill all states with max values of all these clocks */
                        dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
@@ -1918,6 +1917,11 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
                        else
                                dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
 
+                       if (!dram_speed_mts[i] && i > 0)
+                               dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
+                       else
+                               dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
                        /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
                        /* PHYCLK_D18, PHYCLK_D32 */
                        dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;