.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
 };
 
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
+DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
+DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
+
+static struct clk_hw *sm6350_rpmh_clocks[] = {
+       [RPMH_CXO_CLK]          = &sc7280_bi_tcxo.hw,
+       [RPMH_CXO_CLK_A]        = &sc7280_bi_tcxo_ao.hw,
+       [RPMH_LN_BB_CLK2]       = &sm6350_ln_bb_clk2.hw,
+       [RPMH_LN_BB_CLK2_A]     = &sm6350_ln_bb_clk2_ao.hw,
+       [RPMH_LN_BB_CLK3]       = &sm6350_ln_bb_clk3.hw,
+       [RPMH_LN_BB_CLK3_A]     = &sm6350_ln_bb_clk3_ao.hw,
+       [RPMH_QLINK_CLK]        = &sm6350_qlink.hw,
+       [RPMH_QLINK_CLK_A]      = &sm6350_qlink_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
+       .clks = sm6350_rpmh_clocks,
+       .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
                                         void *data)
 {
        { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
        { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
        { .compatible = "qcom,sdx55-rpmh-clk",  .data = &clk_rpmh_sdx55},
+       { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
        { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
        { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
        { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},