Modifications for 1.1.5:
======================================================================
+* Patch by Steven Scholz, 05 Feb 2002:
+ Rename CONFIG_IDE_* #defines to match used in current Linux kernels
+
+* Patch by Frank Panno, 6 Feb 2002:
+ Add support for Embedded Planet EP8260 Board
+ (tested with SBC 8260 H, V.1.1)
+
* Fix initialization of the Super I/O chip on Sandpoint board
* Fix flash driver for PCIPPC2: size for AMD_ID_F040B, comments.
E: frank.morauf@salzbrenner.com
D: Support for Embedded Planet RPX Super Board
+N: Frank Panno
+E: fpanno@delphintech.com
+D: Support for Embedded Planet EP8260 Board
+
N: Denis Peter
E: d.peter@mpl.ch
D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
#########################################################################
LIST_8260=" \
- cogent_mpc8260 gw8260 hymod MPC8260ADS \
- PM826 RPXsuper rsdproto sbc8260 \
- TQM8260 \
+ cogent_mpc8260 ep8260 gw8260 hymod \
+ MPC8260ADS PM826 RPXsuper rsdproto \
+ sbc8260 TQM8260 \
"
#########################################################################
echo "CPU = mpc8260" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+ep8260_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = ep8260" >>config.mk ; \
+ echo "CPU = mpc8260" >>config.mk ;
+ @echo "/* Automatically generated - do not edit */" >include/config.h
+ @echo "#include <config_$(@:_config=).h>" >>include/config.h
+
gw8260_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET)
+ XXX - this list needs to get updated!
+
+ XXX - when using the (yet undocumented) "autoscript"
+ command, be aware that the length of your
+ "script" file is limited by the console bugger
+ size (defined by CFG_CBSIZE in your board
+ config file) - at least if you are NOT using
+ the HUSH shell.
+
- Watchdog:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o mii_phy.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EP8260 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h
+# for the "final" configuration, with ppcboot in flash, or the address
+# in RAM where ppcboot is loaded at for debugging.
+#
+#TEXT_BASE = 0x00100000
+#TEXT_BASE = 0xFF000000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
--- /dev/null
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "ep8260.h"
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
+ /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
+ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
+ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
+ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
+ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
+ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
+ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
+ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
+ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
+ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
+ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
+ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
+ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
+ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
+ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int
+board_pre_init(void)
+{
+ volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ memctl->memc_br4 = CFG_BR4_PRELIM;
+ memctl->memc_or4 = CFG_OR4_PRELIM;
+ regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
+ regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
+ return 0;
+}
+
+void
+reset_phy(void)
+{
+ volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+ regs->bcsr4 = 0xC0;
+}
+
+/*
+ * Check Board Identity:
+ * I don' know, how the next board revisions will be coded.
+ * Thats why its a static interpretation ...
+*/
+
+int
+checkboard(void)
+{
+ volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+ uint major=0, minor=0;
+ switch (regs->bcsr0) {
+ case 0x02: major = 1; break;
+ case 0x03: major = 1; minor = 1; break;
+ default: break;
+ }
+ printf ("Embedded Planet EP8260, Revision %d.%d\n", major, minor);
+ return 1;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+
+long int
+initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar c = 0;
+ volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
+/*
+ ulong psdmr = CFG_PSDMR;
+#ifdef CFG_LSDRAM
+ ulong lsdmr = CFG_LSDMR;
+#endif
+*/
+ long size = CFG_SDRAM0_SIZE;
+ int i;
+
+
+/*
+* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+*
+* "At system reset, initialization software must set up the
+* programmable parameters in the memory controller banks registers
+* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+* system software should execute the following initialization sequence
+* for each SDRAM device.
+*
+* 1. Issue a PRECHARGE-ALL-BANKS command
+* 2. Issue eight CBR REFRESH commands
+* 3. Issue a MODE-SET command to initialize the mode register
+*
+* The initial commands are executed by setting P/LSDMR[OP] and
+* accessing the SDRAM with a single-byte transaction."
+*
+* The appropriate BRx/ORx registers have already been set when we
+* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+*/
+
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+
+#ifndef CFG_RAMBOOT
+#ifdef CFG_LSDRAM
+ size += CFG_SDRAM1_SIZE;
+ ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
+ memctl->memc_lsrt = CFG_LSRT;
+
+ memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+#endif /* CFG_LSDRAM */
+#endif /* CFG_RAMBOOT */
+ return (size * 1024 * 1024);
+}
+
--- /dev/null
+#ifndef __EP8260_H__
+#define __EP8260_H__
+
+typedef struct tt_ep_regs {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+ volatile unsigned char bcsr6;
+ volatile unsigned char bcsr7;
+ volatile unsigned char bcsr8;
+ volatile unsigned char bcsr9;
+ volatile unsigned char bcsr10;
+ volatile unsigned char bcsr11;
+ volatile unsigned char bcsr12;
+ volatile unsigned char bcsr13;
+ volatile unsigned char bcsr14;
+ volatile unsigned char bcsr15;
+} t_ep_regs;
+typedef t_ep_regs *tp_ep_regs;
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * Flash Routines for AMD device AM29DL323DB on the EP8260 board.
+ *
+ * This file is based on board/tqm8260/flash.c.
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a) (*(volatile unsigned long *)( a ))
+#define V_BYTE(a) (*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset(void)
+{
+ if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
+ V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
+ V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size( ulong baseaddr, flash_info_t *info )
+{
+ short i;
+ unsigned long flashtest_h, flashtest_l;
+
+ /* Write auto select command sequence and test FLASH answer */
+ V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+ V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
+ V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
+ V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+ V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
+ V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
+
+ flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */
+ flashtest_l = V_ULONG(baseaddr + 4);
+
+ if ((int)flashtest_h == AMD_MANUFACT) {
+ info->flash_id = FLASH_MAN_AMD;
+ } else {
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ flashtest_h = V_ULONG(baseaddr + 8); /* device ID */
+ flashtest_l = V_ULONG(baseaddr + 12);
+ if (flashtest_h != flashtest_l) {
+ info->flash_id = FLASH_UNKNOWN;
+ return(0);
+ }
+ if (flashtest_h == AMD_ID_DL323B) {
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
+ } else {
+ info->flash_id = FLASH_UNKNOWN;
+ return(0); /* no or unknown flash */
+ }
+
+ /* set up sector start adress table (bottom sector type) */
+ for (i = 0; i < 8; i++) {
+ info->start[i] = baseaddr + (i * 0x00008000);
+ }
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
+ (V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
+ info->protect[i] = 1; /* D0 = 1 if protected */
+ } else {
+ info->protect[i] = 0;
+ }
+ }
+
+ flash_reset();
+ return(info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size_b0 = 0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here (only one bank) */
+
+ size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0>>20);
+ }
+
+ /*
+ * protect monitor and environment sectors
+ */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch ((info->flash_id >> 16) & 0xff) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+ V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
+ V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+ V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+ V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
+ V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ V_ULONG( info->start[sect] ) = 0x00300030;
+ V_ULONG( info->start[sect] + 4 ) = 0x00300030;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
+ (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
+ {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ flash_reset ();
+
+ printf (" done\n");
+ return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong dp;
+ static unsigned char bb[8];
+ int i, l, rc, cc = cnt;
+
+ dp = (addr & ~7); /* get lower dword aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - dp) != 0) {
+ for (i = 0; i < 8; i++)
+ bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
+ if ((rc = write_dword(info, dp, bb)) != 0)
+ {
+ return (rc);
+ }
+ dp += 8;
+ cc -= 8 - l;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cc >= 8) {
+ if ((rc = write_dword(info, dp, src)) != 0) {
+ return (rc);
+ }
+ dp += 8;
+ src += 8;
+ cc -= 8;
+ }
+
+ if (cc <= 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ for (i = 0; i < 8; i++) {
+ bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
+ }
+ return (write_dword(info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
+{
+ ulong start, cl, ch;
+ int flag, i;
+
+ for (i = 0; i < 4; i++)
+ ch = (ch << 8) + *pdata++; /* high word */
+ for (i = 0; i < 4; i++)
+ cl = (cl << 8) + *pdata++; /* low word */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & ch) != ch
+ ||(*((vu_long *)(dest + 4)) & cl) != cl)
+ {
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+ V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
+ V_ULONG( dest ) = ch;
+ V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+ V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+ V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
+ V_ULONG( dest + 4 ) = cl;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
+ ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
--- /dev/null
+#include <ppcboot.h>
+#include "mii_phy.h"
+#include "ep8260.h"
+
+#define MII_MDIO 0x01
+#define MII_MDCK 0x02
+#define MII_MDIR 0x04
+
+void
+mii_discover_phy(void)
+{
+ int known;
+ unsigned short phy_reg;
+ unsigned long phy_id;
+
+ known = 0;
+ printf("Discovering phy @ 0: ");
+ phy_id = mii_phy_read(2) << 16;
+ phy_id |= mii_phy_read(3);
+ if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+ printf("Level One ");
+ if ((phy_id & 0x000003F0) == 0xE0) {
+ printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+ known = 1;
+ }
+ else printf("unknown type\n");
+ }
+ else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+ phy_reg = mii_phy_read(1);
+ if (!(phy_reg & 0x0004)) printf("Link is down\n");
+ if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+ if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+ if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+ if (known) {
+ phy_reg = mii_phy_read(17);
+ if (phy_reg & 0x0400)
+ printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+ phy_reg & 0x4000 ? 100 : 10,
+ phy_reg & 0x0200 ? "full" : "half");
+ else
+ printf("bad link!!\n");
+/*
+left off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+ mii_phy_write(20, 0x0452);
+ }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+ int i;
+ unsigned short tmp, val = 0, adr = 0;
+ t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+
+ tmp = 0x6002 | (adr << 7) | (reg << 2);
+ regs->bcsr4 = 0xC3;
+ for (i = 0; i < 64; i++) {
+ regs->bcsr4 ^= MII_MDCK;
+ }
+ for (i = 0; i < 16; i++) {
+ regs->bcsr4 &= ~MII_MDCK;
+ if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+ else regs->bcsr4 &= ~MII_MDIO;
+ regs->bcsr4 |= MII_MDCK;
+ tmp <<= 1;
+ }
+ regs->bcsr4 |= MII_MDIR;
+ for (i = 0; i < 16; i++) {
+ val <<= 1;
+ regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+ if (regs->bcsr4 & MII_MDIO) val |= 1;
+ regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+ }
+ return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+ int i;
+ unsigned short tmp, adr = 0;
+ t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+
+ tmp = 0x5002 | (adr << 7) | (reg << 2);
+ regs->bcsr4 = 0xC3;
+ for (i = 0; i < 64; i++) {
+ regs->bcsr4 ^= MII_MDCK;
+ }
+ for (i = 0; i < 16; i++) {
+ regs->bcsr4 &= ~MII_MDCK;
+ if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+ else regs->bcsr4 &= ~MII_MDIO;
+ regs->bcsr4 |= MII_MDCK;
+ tmp <<= 1;
+ }
+ for (i = 0; i < 16; i++) {
+ regs->bcsr4 &= ~MII_MDCK;
+ if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+ else regs->bcsr4 &= ~MII_MDIO;
+ regs->bcsr4 |= MII_MDCK;
+ val <<= 1;
+ }
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2001, 2002, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/opt/cross/lib); SEARCH_DIR(/opt/cross/powerpc-linux/lib);
+/* SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); */
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8260/start.o (.text)
+ *(.text)
+/* common/environment.o(.text) */
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS)|| \
defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_EP8260) || \
defined(CONFIG_WALNUT405) || \
defined(CONFIG_W7O)
board_pre_init(); /* very early board init code (fpga boot, etc.) */
#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
defined(CONFIG_CCM) || \
+ defined(CONFIG_EP8260) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
WATCHDOG_RESET();
-# ifdef CONFIG_IDE_PCCARD
+# ifdef CONFIG_IDE_8xx_PCCARD
puts ("PCMCIA:");
# else
puts ("IDE: ");
* MA 02111-1307 USA
*/
-/*
- autoscript allows a remote host to download a command file and, optionally,
- binary data for automatically updating the target. For example, you create
- a new kernel image and want the user to be able to simply download the
- image and the machine does the rest. The kernel image is postprocessed
- with mkimage, which creates an image with a script file prepended. If
- enabled, autoscript will verify the script and contents of the download
- and execute the script portion. This would be responsible for erasing
- flash, copying the new image, and rebooting the machine.
-*/
+/*
+ * autoscript allows a remote host to download a command file and,
+ * optionally, binary data for automatically updating the target. For
+ * example, you create a new kernel image and want the user to be
+ * able to simply download the image and the machine does the rest.
+ * The kernel image is postprocessed with mkimage, which creates an
+ * image with a script file prepended. If enabled, autoscript will
+ * verify the script and contents of the download and execute the
+ * script portion. This would be responsible for erasing flash,
+ * copying the new image, and rebooting the machine.
+ */
#include <ppcboot.h>
#include <command.h>
memcpy (hdr, (char *)addr, sizeof(image_header_t));
- if (hdr->ih_magic != IH_MAGIC)
- {
+ if (hdr->ih_magic != IH_MAGIC) {
printf("Bad magic number\n");
return 1;
}
hdr->ih_hcrc = 0;
len = sizeof(image_header_t);
data = (ulong)hdr;
- if (crc32(0, (char *)data, len) != crc)
- {
+ if (crc32(0, (char *)data, len) != crc) {
printf("Bad header crc\n");
return 1;
}
data = addr + sizeof(image_header_t);
len = hdr->ih_size;
- if (crc32(0, (char *)data, len) != hdr->ih_dcrc)
- {
+ if (crc32(0, (char *)data, len) != hdr->ih_dcrc) {
printf("Bad data crc\n");
return 1;
}
- if (hdr->ih_type != IH_TYPE_SCRIPT)
- {
+ if (hdr->ih_type != IH_TYPE_SCRIPT) {
printf("Bad image type\n");
return 1;
}
/* get len of script and make sure cmd is null terminated */
len_ptr = (ulong *)data;
len = *len_ptr;
- if (len)
- {
- int i;
-
+ if (len) {
cmd = malloc (len + 1);
if (!cmd)
{
while (*len_ptr++);
memcpy(cmd,(char *)len_ptr,len);
*(cmd + len) = 0;
+#ifndef CFG_HUSH_PARSER
/* also (for now) replace \n with ; */
- for (i=0; i<len; i++)
{
- if (cmd[i] == '\n')
- {
- cmd[i] = ';';
+ int i;
+
+ for (i=0; i<len; i++) {
+ if (cmd[i] == '\n') {
+ cmd[i] = ';';
+ }
}
}
+#endif
}
-#ifndef CFG_HUSH_PARSER
+#ifndef CFG_HUSH_PARSER
rcode = run_command(cmd, bd, 0);
#else
- rcode = parse_string_outer(cmd, FLAG_PARSE_SEMICOLON
- | FLAG_EXIT_FROM_LOOP);
-#endif
+ rcode = parse_string_outer(cmd, FLAG_PARSE_SEMICOLON);
+#endif
free(cmd);
return rcode;
}
-#endif
+#endif /* CONFIG_AUTOSCRIPT || CFG_CMD_AUTOSCRIPT */
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
int
ulong addr;
int rcode;
- if (argc < 2)
- {
+ if (argc < 2) {
addr = CFG_LOAD_ADDR;
- }
- else
- {
+ } else {
addr = simple_strtoul(argv[1],0,16);
}
rcode = autoscript(bd,addr);
return rcode;
}
-#endif
-
+#endif /* CFG_CMD_AUTOSCRIPT */
#include <watchdog.h>
#include <command.h>
#include <image.h>
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
# include <pcmcia.h>
#endif
#ifdef CONFIG_8xx
#endif
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
static void set_pcmcia_timing (int pmode);
#else
#define set_pcmcia_timing(a) /* dummy */
case 2:
if (strncmp(argv[1],"res",3) == 0) {
puts ("\nReset IDE"
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
" on PCMCIA " PCMCIA_SLOT_MSG
#endif
": ");
void ide_init (bd_t *bd)
{
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
#endif
unsigned char c;
int i, bus;
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
extern int pcmcia_on (void);
WATCHDOG_RESET();
if (pcmcia_on())
return;
udelay (1000000); /* 1 s */
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
WATCHDOG_RESET();
ide_led ((LED_IDE1 | LED_IDE2), 1); /* LED's on */
ide_reset (); /* ATAPI Drives seems to need a proper IDE Reset */
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
/* PCMCIA / IDE initialization for common mem space */
pcmp->pcmc_pgcrb = 0;
#endif
}
-#ifdef CONFIG_IDE_PCMCIA
+#ifdef CONFIG_IDE_8xx_DIRECT
static void
set_pcmcia_timing (int pmode)
}
-#endif /* CONFIG_IDE_PCMCIA */
+#endif /* CONFIG_IDE_8xx_DIRECT */
/* ------------------------------------------------------------------------- */
#include <config.h>
#include <pcmcia.h>
#include <cmd_pcmcia.h>
-#if defined(CONFIG_IDE_PCCARD) && defined(CONFIG_8xx)
+#if defined(CONFIG_IDE_8xx_PCCARD) && defined(CONFIG_8xx)
#include <mpc8xx.h>
#endif
#if defined(CONFIG_LWMON)
#endif
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
- ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_PCCARD))
+ ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD))
int pcmcia_on (void);
#endif
static int hardware_enable (int slot);
static int voltage_set(int slot, int vcc, int vpp);
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
static void print_funcid (int func);
static void print_fixed (volatile uchar *p);
static int identify (volatile uchar *p);
static int check_ide_device (void);
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
static u_int m8xx_get_graycode(u_int size);
#if 0
win->br = base;
switch (i) {
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
case 0: { /* map attribute memory */
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
| CFG_PCMCIA_TIMING );
break;
}
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
default: /* set to not valid */
win->or = 0;
break;
if (hardware_enable(_slot_))
return (1);
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
if (check_ide_device())
return (1);
#endif
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
#define MAX_TUPEL_SZ 512
#define MAX_FEATURES 4
return (0);
}
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
static void print_funcid (int func)
{
puts (indent);
}
puts (" Card\n");
}
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
static void print_fixed (volatile uchar *p)
{
if (p == NULL)
}
putc ('\n');
}
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_PCCARD
+#ifdef CONFIG_IDE_8xx_PCCARD
#define MAX_IDENT_CHARS 64
#define MAX_IDENT_FIELDS 4
return (0); /* don't know */
}
-#endif /* CONFIG_IDE_PCCARD */
+#endif /* CONFIG_IDE_8xx_PCCARD */
/* ------------------------------------------------------------------------- */
-#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_PCCARD) */
+#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */
#ifndef __PPCBOOT__
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
-#define FLAG_NOT_PARSE_SEMICOLON (1 << 2) /* symbol ';' is common for parser */
#endif
#ifdef __PPCBOOT__
parse_string_outer(str, FLAG_EXIT_FROM_LOOP |
FLAG_PARSE_SEMICOLON);
} else {
- parse_string_outer(str, FLAG_EXIT_FROM_LOOP |
- FLAG_NOT_PARSE_SEMICOLON);
+ parse_string_outer(str, FLAG_EXIT_FROM_LOOP);
}
free(str);
return last_return_code;
#ifndef __PPCBOOT__
int save_num_progs;
#endif
- int rcode=0;
+ int rcode=0, flag_skip=1;
int flag_restore = 0;
int if_code=0, next_if_code=0; /* need double-buffer to handle elif */
reserved_style rmode, skip_more_in_this_rmode=RES_XXXX;
}
rmode = pi->r_mode;
debug_printf("rmode=%d if_code=%d next_if_code=%d skip_more=%d\n", rmode, if_code, next_if_code, skip_more_in_this_rmode);
- if (rmode == skip_more_in_this_rmode) continue;
+ if (rmode == skip_more_in_this_rmode && flag_skip) {
+ if (pi->followup == PIPE_SEQ) flag_skip=0;
+ continue;
+ }
+ flag_skip = 1;
skip_more_in_this_rmode = RES_XXXX;
if (rmode == RES_THEN || rmode == RES_ELSE) if_code = next_if_code;
if (rmode == RES_THEN && if_code) continue;
syntax();
return 1; /* syntax error, groups and arglists don't mix */
}
- if (!child->argv && !(ctx->type & FLAG_NOT_PARSE_SEMICOLON)) {
+ if (!child->argv && (ctx->type & FLAG_PARSE_SEMICOLON)) {
debug_printf("checking %s for reserved-ness\n",dest->data);
if (reserved_word(dest,ctx)) return ctx->w==RES_SNTX;
}
ctx.type = flag;
initialize_context(&ctx);
update_ifs_map();
- if ((flag & FLAG_NOT_PARSE_SEMICOLON)) mapset(";$", 0);
+ if (!(flag & FLAG_PARSE_SEMICOLON)) mapset(";$&|", 0);
inp->promptmode=1;
rcode = parse_stream(&temp, &ctx, inp, '\n');
#ifdef __PPCBOOT__
#else
setup_file_in_str(&input);
#endif
- rcode = parse_stream_outer(&input, 0);
+ rcode = parse_stream_outer(&input, FLAG_PARSE_SEMICOLON);
return rcode;
}
#if (CONFIG_BOOTDELAY >= 0)
static int abortboot(int);
#endif
+
#undef DEBUG_PARSER
char console_buffer[CFG_CBSIZE]; /* console I/O buffer */
int repeatable = 1;
#ifdef DEBUG_PARSER
- printf ("[RUN_COMMAND] cmd[%p]=\"%s\"\n", cmd, cmd ? cmd : "NULL");
+ printf ("[RUN_COMMAND] cmd[%p]=\"", cmd);
+ puts (cmd ? cmd : "NULL"); /* use puts - string may be loooong */
+ puts ("\"\n");
#endif
clear_ctrlc(); /* forget any previous Control C */
- if (!cmd || !*cmd || strlen(cmd) > CFG_CBSIZE - 1)
- return -1; /* empty command or too long, do nothing */
+ if (!cmd || !*cmd) {
+ return -1; /* empty command */
+ }
+
+ if (strlen(cmd) >= CFG_CBSIZE) {
+ puts ("## Command too long!\n");
+ return -1;
+ }
strcpy (cmdbuf, cmd);
static struct b_lists g_1PassList;
-#define DEBUG(x...)
+#ifdef DEBUG
+# define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+# define DEBUGF(fmt,args...)
+#endif
+
#define MALLOC_CHUNK (10*1024)
// if we have no list, we need to rescan
if (pL->fragListCount == 0) {
- DEBUG("rescan: fraglist zero\n");
+ DEBUGF ("rescan: fraglist zero\n");
return 1;
}
// or if we are scanninga new partition
if (pL->partOffset != part->offset) {
- DEBUG("rescan: different partition\n");
+ DEBUGF ("rescan: different partition\n");
return 1;
}
// but suppose someone reflashed the root partition at the same offset...
while (b) {
node = (struct jffs2_unknown_node *) (b->offset);
if (node->nodetype != JFFS2_NODETYPE_DIRENT) {
- DEBUG("rescan: fs changed beneath me? (%lx)\n", (unsigned long) b->offset);
+ DEBUGF ("rescan: fs changed beneath me? (%lx)\n", (unsigned long) b->offset);
return 1;
}
b = b->next;
return 0;
}
- DEBUG(printf("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname,
- (unsigned long) dest, ret));
+ DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname,
+ (unsigned long) dest, ret);
return ret;
}
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCMCIA 1 /* PCMCIA interface required */
+#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#undef CONFIG_IDE_LED /* LED for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
/*
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
* External peripheral base address
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#if 1
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
/* Print Buffer Size
*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_DOS_PARTITION 1
#define CONFIG_ISO_PARTITION 1
#undef CONFIG_ATAPI
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCMCIA 1 /* PCMCIA interface required */
+#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCMCIA 1 /* PCMCIA interface required */
+#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported... */
#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported... */
#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCMCIA 1 /* PCMCIA interface required */
+#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_LED 1 /* LED for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
* External peripheral base address
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * This file is based on similar values for other boards found in other
+ * ppcboot config files, and some that I found in the EP8260 manual.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ *
+ * Note: my board is a "SBC 8260 H, V.1.1"
+ * - 64M 60x Bus SDRAM
+ * - 32M Local Bus SDRAM
+ * - 16M Flash (4 x AM29DL323DB90WDI)
+ * - 128k NVRAM with RTC
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H MODCK[1-3] Osc CPM Core
+ * ------- ---------- --- --- ----
+ * 0x2 0x2 33 133 133
+ * 0x2 0x3 33 133 166
+ * 0x2 0x4 33 133 200
+ * 0x2 0x5 33 133 233
+ * 0x2 0x6 33 133 266
+ *
+ * 0x5 0x5 66 133 133
+ * 0x5 0x6 66 133 166
+ * 0x5 0x7 66 133 200 *
+ * 0x6 0x0 66 133 233
+ * 0x6 0x1 66 133 266
+ * 0x6 0x2 66 133 300
+ */
+#define CFG_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let PPCBOOT live at 0x00000000.
+ */
+/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */
+/* #undef CFG_SBC_BOOT_LOW */
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. PPCBOOT expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0xFF000000
+#define CFG_FLASH0_SIZE 16
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6. PPCBOOT expects this to be the on board FLASH. If you don't
+ * want it enabled, don't define these constants.
+ */
+#define CFG_FLASH1_BASE 0
+#define CFG_FLASH1_SIZE 0
+#undef CFG_FLASH1_BASE
+#undef CFG_FLASH1_SIZE
+
+/* What should be the base address of SDRAM DIMM (60x bus) and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/* undefine CFG_LSDRAM if you don't want to enable the 32M SDRAM on the
+ * local bus
+*/
+#define CFG_LSDRAM
+/* #undef CFG_LSDRAM */
+
+#ifdef CFG_LSDRAM
+/* What should be the base address of SDRAM DIMM (local bus) and how big is
+ * it (in Mbytes)?
+*/
+ #define CFG_SDRAM1_BASE 0x04000000
+ #define CFG_SDRAM1_SIZE 32
+#else
+ #define CFG_SDRAM1_BASE 0
+ #define CFG_SDRAM1_SIZE 0
+ #undef CFG_SDRAM1_BASE
+ #undef CFG_SDRAM1_SIZE
+#endif /* CFG_LSDRAM */
+
+/* What should be the base address of NVRAM and how big is
+ * it (in Bytes)
+ */
+#define CFG_NVRAM_BASE_ADDR 0xFa080000
+#define CFG_NVRAM_SIZE (128*1024)-16
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0x00000000
+#undef CFG_LED_BASE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC /* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on neither */
+#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
+#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
+#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
+
+#if ( CONFIG_ETHER_INDEX == 3 )
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/*
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ */
+#ifdef CFG_LSDRAM
+ #define CFG_CPMFCR_RAMTYPE 3
+#else /* CFG_LSDRAM */
+ #define CFG_CPMFCR_RAMTYPE 0
+#endif /* CFG_LSDRAM */
+
+/* - Enable Half Duplex in FSMR */
+/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CFG_FCC_PSMR 0
+
+#else /* CONFIG_ETHER_INDEX */
+# error "on EP8260 ethernet must be FCC3"
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_I2C 1
+/* #define CONFIG_RTC_DS174x */
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as ppcboot, and changing variables
+ * will erase ppcboot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+/* #define CONFIG_BAUDRATE 57600 */
+#define CONFIG_BAUDRATE 115200
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR 00:10:EC:00:30:8C
+
+#define CONFIG_IPADDR 192.168.254.130
+#define CONFIG_SERVERIP 192.168.254.49
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY -1
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT "=> "
+
+/* Define this variable to enable the "hush" shell (from
+ Busybox) as command line interpreter, thus enabling
+ powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
+ If undefined, you get the old, much simpler behaviour
+ with a somewhat smapper memory footprint.
+*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* What ppcboot subsytems do you want enabled? */
+/*
+*/
+#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
+ ~CFG_CMD_BSP & \
+ ~CFG_CMD_DATE & \
+ ~CFG_CMD_DCR & \
+ ~CFG_CMD_DHCP & \
+ ~CFG_CMD_DOC & \
+ ~CFG_CMD_EEPROM & \
+ ~CFG_CMD_FDC & \
+ ~CFG_CMD_IDE & \
+ ~CFG_CMD_JFFS2 & \
+ ~CFG_CMD_KGDB & \
+ ~CFG_CMD_MII & \
+ ~CFG_CMD_PCI & \
+ ~CFG_CMD_PCMCIA & \
+ ~CFG_CMD_SCSI & \
+ ~CFG_CMD_USB )
+
+/* Where do the internal registers live? */
+#define CFG_IMMR 0xF0000000
+#define CFG_DEFAULT_IMMR 0x00010000
+
+/* Where do the on board registers (CS4) live? */
+#define CFG_REGS_BASE 0xFA000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
+#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS 8 /* max number of command args */
+
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#ifdef CFG_LSDRAM
+ #define CFG_MEMTEST_START 0x04000000 /* memtest works on */
+ #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
+#else
+ #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+ #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
+#endif /* CFG_LSDRAM */
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE CFG_FLASH0_BASE
+#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+
+#if defined(CFG_SBC_BOOT_LOW)
+# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
+#else
+# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+/*
+#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
+ ((CFG_IMMR & 0x01000000) >> 7) |\
+ ((CFG_IMMR & 0x00100000) >> 4) )
+
+#define CFG_HRCW_MASTER (HRCW_EBM |\
+ HRCW_L2CPC01 |\
+ CFG_SBC_HRCW_IMMR |\
+ HRCW_APPC10 |\
+ HRCW_CS10PC01 |\
+ HRCW_MODCK_H0101 |\
+ CFG_SBC_HRCW_BOOT_FLAGS)
+*/
+#define CFG_HRCW_MASTER 0x10400245
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 128 /* bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+
+#ifndef CFG_RAMBOOT
+# define CFG_ENV_IS_IN_FLASH 1
+
+# ifdef CFG_ENV_IN_OWN_SECT
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+# define CFG_ENV_SECT_SIZE 0x40000
+# else
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
+# endif /* CFG_ENV_IN_OWN_SECT */
+#else
+# define CFG_ENV_IS_IN_NVRAM 1
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+# define CFG_ENV_SIZE 0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT (/*HID0_ICE |*/\
+ /*HID0_DCE |*/\
+ HID0_ICFI |\
+ HID0_DCI |\
+ HID0_IFEM |\
+ HID0_ABE)
+
+#define CFG_HID0_FINAL (/*HID0_ICE |*/\
+ HID0_IFEM |\
+ HID0_ABE |\
+ HID0_EMCP)
+#define CFG_HID2 0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR 0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration 4-25
+ *-----------------------------------------------------------------------
+ */
+/*#define CFG_BCR (BCR_EBM |\
+ BCR_PLDP |\
+ BCR_EAV |\
+ BCR_NPQM1)
+*/
+#define CFG_BCR 0x80C08000
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
+ SIUMCR_APPC10 |\
+ SIUMCR_CS10PC01)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#ifdef CFG_LSDRAM
+#define CFG_SYPCR (SYPCR_SWTC |\
+ SYPCR_BMT |\
+ SYPCR_PBME |\
+ SYPCR_LBME |\
+ SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC |\
+ SYPCR_BMT |\
+ SYPCR_PBME |\
+ SYPCR_SWP)
+#endif
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC |\
+ TMCNTSC_ALR |\
+ TMCNTSC_TCF |\
+ TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+/*#define CFG_PISCR (PISCR_PS |\
+ PISCR_PTF |\
+ PISCR_PTE)*/
+#define CFG_PISCR 0
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR (SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescale Register 10-32
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus Machine PortSz Device
+ * ---- --- ------- ------ ------
+ * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
+ * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
+ * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
+ * 3 unused
+ * 4 60x GPCM 8 bit Board Regs, NVRTC
+ * 5 unused
+ * 6 unused
+ * 7 unused
+ * 8 PCMCIA
+ * 9 unused
+ * 10 unused
+ * 11 unused
+*/
+
+/*-----------------------------------------------------------------------
+ * BRx - Base Register
+ * Ref: Section 10.3.1 on page 10-14
+ * ORx - Option Register
+ * Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - FLASH
+ *
+ */
+#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_DECC_NONE |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_6_CLK |\
+ ORxG_EHTR)
+
+/* Bank 1 - SDRAM
+ * PSDRAM
+ */
+#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A6 |\
+ ORxS_NUMR_12)
+
+#define CFG_PSDMR 0xC34E2462
+#define CFG_PSRT 0x64
+
+
+#ifdef CFG_LSDRAM
+/* Bank 2 - SDRAM
+ * LSDRAM
+ */
+
+ #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+ BRx_PS_32 |\
+ BRx_MS_SDRAM_L |\
+ BRx_V)
+
+ #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A9 |\
+ ORxS_NUMR_12)
+
+ #define CFG_LSDMR 0x416A2562
+ #define CFG_LSRT 0x64
+#else
+ #define CFG_LSRT 0x0
+#endif /* CFG_LSDRAM */
+
+/* Bank 4 - On board registers
+ * NVRTC and BCSR
+ */
+#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_10_CLK |\
+ ORxG_TRLX)
+
+/* Bank 8 - On board registers
+ * PCMCIA (currently not working!)
+ */
+#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CFG_OR8_PRELIM (ORxG_AM_MSK |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SETA |\
+ ORxG_SCY_10_CLK)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
*-----------------------------------------------------------------------
*/
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
-#define FLAG_NOT_PARSE_SEMICOLON (1 << 2) /* symbol ';' is common for parser */
+#define FLAG_NOT_PARSE_SEMICOLON (1 << 2) /* symbol ';' is special for parser */
extern int ppcboot_hush_start(bd_t *bd);
extern int parse_string_outer(char *s, int flag);
*/
#if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
((CONFIG_COMMANDS & CFG_CMD_IDE) && \
- (defined(CONFIG_IDE_PCCARD) || defined(CONFIG_IDE_PCMCIA) ) )
+ (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
#define CISTPL_IDE_HAS_INDEX 0x20
#define CISTPL_IDE_IOIS16 0x40
-#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE&&(CONFIG_IDE_PCCARD||CONFIG_IDE_PCMCIA) */
+#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
#endif /* _PCMCIA_H */
#endif
#if defined(CONFIG_CCM) || \
+ defined(CONFIG_EP8260) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
void load_sernum_ethaddr(bd_t *bd);
#endif
-#if defined(CONFIG_CPCI405) || \
+#if defined(CONFIG_ADCIOP) || \
defined(CONFIG_AR405) || \
defined(CONFIG_CANBT) || \
- defined(CONFIG_WALNUT405) || \
- defined(CONFIG_PIP405) || \
- defined(CONFIG_MIP405) || \
+ defined(CONFIG_CPCI405) || \
defined(CONFIG_CPCIISER4) || \
- defined(CONFIG_OCRTC) || \
- defined(CONFIG_ADCIOP) || \
+ defined(CONFIG_CU824) || \
defined(CONFIG_DASA_SIM) || \
+ defined(CONFIG_EP8260) || \
defined(CONFIG_LWMON) || \
+ defined(CONFIG_MIP405) || \
defined(CONFIG_MPC8260ADS) || \
+ defined(CONFIG_OCRTC) || \
+ defined(CONFIG_PIP405) || \
defined(CONFIG_RPXSUPER) || \
- defined(CONFIG_CU824) || \
defined(CONFIG_W7O) || \
+ defined(CONFIG_WALNUT405) || \
defined(CONFIG_BOARD_PRE_INIT)
/* $(BOARD)/$(BOARD).c */
int board_pre_init (void);
projects / users / rw / ppcboot.git / commitdiff