drm/amd/display: Update dcn351 to latest dcn35 config

[why & how]
There were some fixes in dcn35 that need
to be ported over to dcn351 to prevent any
regression.

Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Reviewed-by: Liu, Xi (Alex) <xiliu102@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index b6246406a04232604ef84076e353ef1e82006309..b3ffab77cf889487f7024c22eb4a18542c7bfbea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -402,6 +402,8 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
                                clock_limits[i].socclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
                                clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
+                               clock_limits[i].dtbclk_mhz;
                        dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
                                clk_table->num_entries;
                        dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
@@ -414,6 +416,8 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
                                clk_table->num_entries;
                        dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
                                clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
+                               clk_table->num_entries;
                }
        }
 
@@ -613,6 +617,7 @@ void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)
                if (context->res_ctx.pipe_ctx[i].plane_state)
                        plane_count++;
        }
+
        /*dcn351 does not support z9/z10*/
        if (context->stream_count == 0 || plane_count == 0) {
                support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
@@ -626,11 +631,9 @@ void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)
                        dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
                bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
 
-
                /*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/
-                if (is_pwrseq0 && (is_psr || is_replay))
+               if (is_pwrseq0 && (is_psr || is_replay))
                        support = allow_z8 ? allow_z8 : DCN_ZSTATE_SUPPORT_DISALLOW;
-
        }
        context->bw_ctx.bw.dcn.clk.zstate_support = support;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index ab17fa1c64e8c5b405ae2f24a93c1ee54abefe10..670255c9bc82287fd39474400874059fa13dc557 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -67,7 +67,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
        .prepare_bandwidth = dcn35_prepare_bandwidth,
        .optimize_bandwidth = dcn35_optimize_bandwidth,
        .update_bandwidth = dcn20_update_bandwidth,
-       .set_drr = dcn10_set_drr,
+       .set_drr = dcn35_set_drr,
        .get_position = dcn10_get_position,
        .set_static_screen_control = dcn35_set_static_screen_control,
        .setup_stereo = dcn10_setup_stereo,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 2dfd73d5f767615f8d489f3eace8a902504cff54..fe13c891879b398c29149ae3f829650141ba752c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -700,6 +700,8 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_dcc = DCC_ENABLE,
        .disable_dpp_power_gate = true,
        .disable_hubp_power_gate = true,
+       .disable_optc_power_gate = true, /*should the same as above two*/
+       .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
        .disable_clock_gate = false,
        .disable_dsc_power_gate = true,
        .vsr_support = true,
@@ -742,12 +744,13 @@ static const struct dc_debug_options debug_defaults_drv = {
        },
        .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
        .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
+       .minimum_z8_residency_time = 2100,
        .using_dml2 = true,
        .support_eDP1_5 = true,
        .enable_hpo_pg_support = false,
        .enable_legacy_fast_update = true,
        .enable_single_display_2to1_odm_policy = true,
-       .disable_idle_power_optimizations = true,
+       .disable_idle_power_optimizations = false,
        .dmcub_emulation = false,
        .disable_boot_optimizations = false,
        .disable_unbounded_requesting = false,
@@ -758,8 +761,10 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_z10 = true,
        .ignore_pg = true,
        .psp_disabled_wa = true,
-       .ips2_eval_delay_us = 200,
-       .ips2_entry_delay_us = 400
+       .ips2_eval_delay_us = 2000,
+       .ips2_entry_delay_us = 800,
+       .disable_dmub_reallow_idle = true,
+       .static_screen_wait_frames = 2,
 };
 
 static const struct dc_panel_config panel_config_defaults = {