]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/amdgpu: add convert for new gfx type
authorLikun Gao <Likun.Gao@amd.com>
Wed, 26 Jan 2022 12:07:08 +0000 (20:07 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:43:53 +0000 (10:43 -0400)
Add convert for CP RS64 related gfx ip type.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

index ac8a2876dfd4ddaa30b30677bff7f7019f850e20..7f9ab12ae1ab2772e9ab567b8ebf71c7ad0a3614 100644 (file)
@@ -2211,6 +2211,39 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_IMU_D:
                *type = GFX_FW_TYPE_IMU_D;
                break;
+       case AMDGPU_UCODE_ID_CP_RS64_PFP:
+               *type = GFX_FW_TYPE_RS64_PFP;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_ME:
+               *type = GFX_FW_TYPE_RS64_ME;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_MEC:
+               *type = GFX_FW_TYPE_RS64_MEC;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
+               *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
+               *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
+               *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
+               *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
+               *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
+               *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
+               *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
+               break;
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
+               *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
+               break;
        case AMDGPU_UCODE_ID_MAXIMUM:
        default:
                return -EINVAL;
index 127c034202a9195c735d5cadf73ae51dc2b729a2..273432b75fdacc65874cd9bcc9bfa8c6f5871a59 100644 (file)
@@ -389,6 +389,17 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_CP_CE,
        AMDGPU_UCODE_ID_CP_PFP,
        AMDGPU_UCODE_ID_CP_ME,
+       AMDGPU_UCODE_ID_CP_RS64_PFP,
+       AMDGPU_UCODE_ID_CP_RS64_ME,
+       AMDGPU_UCODE_ID_CP_RS64_MEC,
+       AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
+       AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
        AMDGPU_UCODE_ID_CP_MEC1,
        AMDGPU_UCODE_ID_CP_MEC1_JT,
        AMDGPU_UCODE_ID_CP_MEC2,