ARM: tegra: Correct PL310 Auxiliary Control Register initialization

commit 35509737c8f958944e059d501255a0bf18361ba0 upstream.

The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.

This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:

	L2C-310: enabling full line of zeros but not enabled in Cortex-A9

Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index e512e606eabdd74888a1810e8e1c1a79faa404a8..5ea3421fa1e8c2eef77e0a1aba7126dce33472b3 100644 (file)
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -106,8 +106,8 @@ static const char * const tegra_dt_board_compat[] = {
 };
 
 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
-       .l2c_aux_val    = 0x3c400001,
-       .l2c_aux_mask   = 0xc20fc3fe,
+       .l2c_aux_val    = 0x3c400000,
+       .l2c_aux_mask   = 0xc20fc3ff,
        .smp            = smp_ops(tegra_smp_ops),
        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,