drm/i915: Show LTTPR in the TPS debug print

Indicate which LTTPR we're currently attempting to train when
we print which training pattern we're using.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211004170535.4173-3-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 60ae2ba520069748b1cfa56025b3607563687572..85a09c3e09e87fcb9ab7c4ae838e6d830e85b7f4 100644 (file)
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -637,7 +637,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
        /* enable with pattern 1 (as per spec) */
 
        intel_dp_program_link_training_pattern(intel_dp, crtc_state,
-                                              DP_TRAINING_PATTERN_1);
+                                              DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
 
        /*
         * Magic for VLV/CHV. We _must_ first set up the register

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a45569b8c959e723b4cae9bb58127a801083c139..6bab097cafd2839871d8408864d9b9be3e52365a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -376,7 +376,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
        int len;
 
        intel_dp_program_link_training_pattern(intel_dp, crtc_state,
-                                              dp_train_pat);
+                                              dp_phy, dp_train_pat);
 
        buf[0] = dp_train_pat;
        /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
@@ -404,17 +404,20 @@ static char dp_training_pattern_name(u8 train_pat)
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
                                       const struct intel_crtc_state *crtc_state,
+                                      enum drm_dp_phy dp_phy,
                                       u8 dp_train_pat)
 {
        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
+       char phy_name[10];
 
        if (train_pat != DP_TRAINING_PATTERN_DISABLE)
                drm_dbg_kms(&dev_priv->drm,
-                           "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
+                           "[ENCODER:%d:%s] Using DP training pattern TPS%c, at %s\n",
                            encoder->base.base.id, encoder->base.name,
-                           dp_training_pattern_name(train_pat));
+                           dp_training_pattern_name(train_pat),
+                           intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
 
        intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
@@ -855,7 +858,7 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
        intel_dp->link_trained = true;
 
        intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
-       intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+       intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
                                               DP_TRAINING_PATTERN_DISABLE);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 9d24d594368c53967902a2f63a633622ca1838c5..6a3a7b37349a15d58e1f94a3d15ed602463a1903 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -19,6 +19,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
                               const u8 link_status[DP_LINK_STATUS_SIZE]);
 void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
                                            const struct intel_crtc_state *crtc_state,
+                                           enum drm_dp_phy dp_phy,
                                            u8 dp_train_pat);
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
                                const struct intel_crtc_state *crtc_state,