return cs;
 }
 
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 {
        return __gen2_emit_breadcrumb(rq, cs, 16, 8);
 }
        return 0;
 }
 
-int gen3_emit_bb_start(struct i915_request *rq,
+int gen2_emit_bb_start(struct i915_request *rq,
                       u64 offset, u32 len,
                       unsigned int dispatch_flags)
 {
        return 0;
 }
 
-void gen3_irq_enable(struct intel_engine_cs *engine)
+void gen2_irq_enable(struct intel_engine_cs *engine)
 {
        engine->i915->irq_mask &= ~engine->irq_enable_mask;
        intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
        intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
 }
 
-void gen3_irq_disable(struct intel_engine_cs *engine)
+void gen2_irq_disable(struct intel_engine_cs *engine)
 {
        engine->i915->irq_mask |= engine->irq_enable_mask;
        intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
 
 int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);
 int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);
 
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs);
+u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs);
 u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);
 
 int i830_emit_bb_start(struct i915_request *rq,
                       u64 offset, u32 len,
                       unsigned int dispatch_flags);
-int gen3_emit_bb_start(struct i915_request *rq,
+int gen2_emit_bb_start(struct i915_request *rq,
                       u64 offset, u32 len,
                       unsigned int dispatch_flags);
 int gen4_emit_bb_start(struct i915_request *rq,
                       u64 offset, u32 length,
                       unsigned int dispatch_flags);
 
-void gen3_irq_enable(struct intel_engine_cs *engine);
-void gen3_irq_disable(struct intel_engine_cs *engine);
+void gen2_irq_enable(struct intel_engine_cs *engine);
+void gen2_irq_disable(struct intel_engine_cs *engine);
 void gen5_irq_enable(struct intel_engine_cs *engine);
 void gen5_irq_disable(struct intel_engine_cs *engine);
 
 
                engine->irq_enable = gen5_irq_enable;
                engine->irq_disable = gen5_irq_disable;
        } else {
-               engine->irq_enable = gen3_irq_enable;
-               engine->irq_disable = gen3_irq_disable;
+               engine->irq_enable = gen2_irq_enable;
+               engine->irq_disable = gen2_irq_disable;
        }
 }
 
         * equivalent to our next initial bread so we can elide
         * engine->emit_init_breadcrumb().
         */
-       engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
+       engine->emit_fini_breadcrumb = gen2_emit_breadcrumb;
        if (GRAPHICS_VER(i915) == 5)
                engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
 
        else if (IS_I830(i915) || IS_I845G(i915))
                engine->emit_bb_start = i830_emit_bb_start;
        else
-               engine->emit_bb_start = gen3_emit_bb_start;
+               engine->emit_bb_start = gen2_emit_bb_start;
 }
 
 static void setup_rcs(struct intel_engine_cs *engine)