--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL            0x000
+#define MERGE_EN                               1
+#define DISP_REG_MERGE_CFG_0           0x010
+#define DISP_REG_MERGE_CFG_4           0x020
+#define DISP_REG_MERGE_CFG_10          0x038
+/* no swap */
+#define SWAP_MODE                              0
+#define FLD_SWAP_MODE                          GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12          0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE             6
+#define CFG_10_10_2PI_2PO_BUF_MODE             8
+#define FLD_CFG_MERGE_MODE                     GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24          0x070
+#define DISP_REG_MERGE_CFG_25          0x074
+#define DISP_REG_MERGE_CFG_36          0x0a0
+#define ULTRA_EN                               BIT(0)
+#define PREULTRA_EN                            BIT(4)
+#define DISP_REG_MERGE_CFG_37          0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE                            3
+#define FLD_BUFFER_MODE                                GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40          0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW                           (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH                          (8 * 594)
+#define FLD_ULTRA_TH_LOW                       GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH                      GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41          0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW                                (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH                       (9 * 594)
+#define FLD_PREULTRA_TH_LOW                    GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH                   GENMASK(31, 16)
+
+struct mtk_disp_merge {
+       void __iomem                    *regs;
+       struct clk                      *clk;
+       struct clk                      *async_clk;
+       struct cmdq_client_reg          cmdq_reg;
+       bool                            fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+                                  struct cmdq_pkt *cmdq_pkt)
+{
+       mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+                     &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+       mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+                          FLD_BUFFER_MODE);
+
+       mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+       mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+                          FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+                     unsigned int h, unsigned int vrefresh,
+                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+       if (!h || !w) {
+               dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+               return;
+       }
+
+       if (priv->fifo_en) {
+               mtk_merge_fifo_setting(priv, cmdq_pkt);
+               mode = CFG_10_10_2PI_2PO_BUF_MODE;
+       }
+
+       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+                     DISP_REG_MERGE_CFG_0);
+       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+                     DISP_REG_MERGE_CFG_4);
+       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+                     DISP_REG_MERGE_CFG_24);
+       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+                     DISP_REG_MERGE_CFG_25);
+       mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+       mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+                          DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+       int ret = 0;
+       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+       ret = clk_prepare_enable(priv->clk);
+       if (ret) {
+               dev_err(dev, "merge clk prepare enable failed\n");
+               return ret;
+       }
+
+       ret = clk_prepare_enable(priv->async_clk);
+       if (ret) {
+               /* should clean up the state of priv->clk */
+               clk_disable_unprepare(priv->clk);
+
+               dev_err(dev, "async clk prepare enable failed\n");
+               return ret;
+       }
+
+       return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+       clk_disable_unprepare(priv->async_clk);
+       clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+                              void *data)
+{
+       return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+                                 void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+       .bind   = mtk_disp_merge_bind,
+       .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct resource *res;
+       struct mtk_disp_merge *priv;
+       int ret;
+
+       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+       if (!priv)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       priv->regs = devm_ioremap_resource(dev, res);
+       if (IS_ERR(priv->regs)) {
+               dev_err(dev, "failed to ioremap merge\n");
+               return PTR_ERR(priv->regs);
+       }
+
+       priv->clk = devm_clk_get(dev, NULL);
+       if (IS_ERR(priv->clk)) {
+               dev_err(dev, "failed to get merge clk\n");
+               return PTR_ERR(priv->clk);
+       }
+
+       priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+       if (IS_ERR(priv->async_clk)) {
+               dev_err(dev, "failed to get merge async clock\n");
+               return PTR_ERR(priv->async_clk);
+       }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+       if (ret)
+               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+       priv->fifo_en = of_property_read_bool(dev->of_node,
+                                             "mediatek,merge-fifo-en");
+
+       platform_set_drvdata(pdev, priv);
+
+       ret = component_add(dev, &mtk_disp_merge_component_ops);
+       if (ret != 0)
+               dev_err(dev, "Failed to add component: %d\n", ret);
+
+       return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+       return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+       { .compatible = "mediatek,mt8195-disp-merge", },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+       .probe = mtk_disp_merge_probe,
+       .remove = mtk_disp_merge_remove,
+       .driver = {
+               .name = "mediatek-disp-merge",
+               .owner = THIS_MODULE,
+               .of_match_table = mtk_disp_merge_driver_dt_match,
+       },
+};
 
        .stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+       .clk_enable = mtk_merge_clk_enable,
+       .clk_disable = mtk_merge_clk_disable,
+       .start = mtk_merge_start,
+       .stop = mtk_merge_stop,
+       .config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
        .clk_enable = mtk_ddp_clk_enable,
        .clk_disable = mtk_ddp_clk_disable,
        [MTK_DISP_DITHER] = "dither",
        [MTK_DISP_DSC] = "dsc",
        [MTK_DISP_GAMMA] = "gamma",
+       [MTK_DISP_MERGE] = "merge",
        [MTK_DISP_MUTEX] = "mutex",
        [MTK_DISP_OD] = "od",
        [MTK_DISP_OVL] = "ovl",
        [DDP_COMPONENT_DSI2]            = { MTK_DSI,            2, &ddp_dsi },
        [DDP_COMPONENT_DSI3]            = { MTK_DSI,            3, &ddp_dsi },
        [DDP_COMPONENT_GAMMA]           = { MTK_DISP_GAMMA,     0, &ddp_gamma },
+       [DDP_COMPONENT_MERGE0]          = { MTK_DISP_MERGE,     0, &ddp_merge },
+       [DDP_COMPONENT_MERGE1]          = { MTK_DISP_MERGE,     1, &ddp_merge },
+       [DDP_COMPONENT_MERGE2]          = { MTK_DISP_MERGE,     2, &ddp_merge },
+       [DDP_COMPONENT_MERGE3]          = { MTK_DISP_MERGE,     3, &ddp_merge },
+       [DDP_COMPONENT_MERGE4]          = { MTK_DISP_MERGE,     4, &ddp_merge },
+       [DDP_COMPONENT_MERGE5]          = { MTK_DISP_MERGE,     5, &ddp_merge },
        [DDP_COMPONENT_OD0]             = { MTK_DISP_OD,        0, &ddp_od },
        [DDP_COMPONENT_OD1]             = { MTK_DISP_OD,        1, &ddp_od },
        [DDP_COMPONENT_OVL0]            = { MTK_DISP_OVL,       0, &ddp_ovl },
            type == MTK_DISP_CCORR ||
            type == MTK_DISP_COLOR ||
            type == MTK_DISP_GAMMA ||
+           type == MTK_DISP_MERGE ||
            type == MTK_DISP_OVL ||
            type == MTK_DISP_OVL_2L ||
            type == MTK_DISP_PWM ||