drm/i915: Move load time IRQ SW init earlier

Most of the IRQ init is setting up hooks so move that part earlier.
Leave the pm_qos_add_request() call in place.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1458128348-15730-4-git-send-email-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c79f53292a6fba4f992092cad934bdd1c803c70b..e23cdadc1bee4721b724735916fb0a428e0fa388 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1026,6 +1026,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        intel_pm_setup(dev);
        intel_init_dpio(dev_priv);
        intel_power_domains_init(dev_priv);
+       intel_irq_init(dev_priv);
 
        intel_runtime_pm_get(dev_priv);
 
@@ -1100,7 +1101,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
                                              aperture_size);
 
-       intel_irq_init(dev_priv);
+       pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
+                          PM_QOS_DEFAULT_VALUE);
+
        intel_uncore_sanitize(dev);
 
        intel_opregion_setup(dev);

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0f61ae0ff60907c855397f60ea93e3313a2c03f4..8f3e3309c3ab553f4f4cc82d72d084a9f997e8e4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4565,8 +4565,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
        INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
                          i915_hangcheck_elapsed);
 
-       pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
-
        if (IS_GEN2(dev_priv)) {
                dev->max_vblank_count = 0;
                dev->driver->get_vblank_counter = i8xx_get_vblank_counter;