Modifications for 1.1.6:
======================================================================
+* Add support for OXC board
+
+* modify 824x I2C driver to allow reading from I2C I/O expanders
+
+* Fix MII speed computation for 8xx Fast Ethernet Controller
+ (Pierre Aubert, 26 Apr 2002)
+
+* Add iopinfo / iopset commands to manipulate (8260) port pins
+ (Brad Kemp, 18 Apr 2002)
+
+* Write CFG_PGMAX when defined (on 824x)
+ (Dustin Byford, Jim Thompson, 14 Apr 2002)
+
* Add support for XIP images
* Patch by Denis Peter, 25 Apr 2002:
(Guillaume Alexandre, 19 Apr 2002)
* Fix flash driver for CU824 Board: set flash write enable bits in
- Board Crontrol Reg.
+ Board Control Reg.
* Modify DOC support to allow for an optional offset into the binary
partition, so that we can store more than one kernel image there.
#########################################################################
LIST_824x=" \
- CU824 MOUSSE MUSENKI \
+ CU824 MOUSSE MUSENKI OXC \
Sandpoint8240 Sandpoint8245 \
"
echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+OXC_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = oxc" >>config.mk ; \
+ echo "CPU = mpc824x" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
Sandpoint8240_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' \) -print \
| xargs rm -f
- rm -f examples/hello_world examples/timer
+ rm -f examples/hello_world examples/timer examples/eepro100_eeprom
rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
rm -f tools/easylogo/easylogo tools/bmp_logo
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# OXC boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for STM29W320DB flash chips
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ size = flash_get_size((vu_char *)CFG_FLASH0_BASE, &flash_info[0]);
+ if (!size || (flash_info[0].flash_id != FLASH_STM800DB &&
+ flash_info[0].flash_id != FLASH_STM800DT))
+ {
+ size = flash_get_size((vu_char *)CFG_FLASH1_BASE, &flash_info[0]);
+ }
+
+#if (CFG_MONITOR_BASE >= CFG_FLASH0_BASE) || \
+ (CFG_MONITOR_BASE >= CFG_FLASH1_BASE)
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id >> 16) {
+ case 0x20:
+ printf ("ST ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_STM320DB:
+ printf ("M29W320DB (32 Mbit)\n");
+ break;
+ case FLASH_STM800DB:
+ printf ("M29W800DB (8 Mbit, bottom boot block)\n");
+ break;
+ case FLASH_STM800DT:
+ printf ("M29W800DT (8 Mbit, top boot block)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+ short i;
+ uchar vendor, devid;
+ ulong base = (ulong)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+ addr[0x0AAA] = 0x90;
+
+ udelay(1000);
+
+ vendor = addr[0];
+ devid = addr[2];
+
+ /* only support STM */
+ if (vendor != 0x20) {
+ return 0;
+ }
+
+ if (devid == FLASH_STM320DB) {
+ /* MPC8240 can address maximum 2Mb of flash, that is why the MSB
+ * lead is grounded and we can access only 2 first Mb */
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 32;
+ info->size = info->sector_count * 0x10000;
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + i * 0x10000;
+ }
+ }
+ else if (devid == FLASH_STM800DB) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 19;
+ info->size = 0x100000;
+ info->start[0] = 0x0000;
+ info->start[1] = 0x4000;
+ info->start[2] = 0x6000;
+ info->start[3] = 0x8000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i-3) * 0x10000;
+ }
+ }
+ else if (devid == FLASH_STM800DT) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 19;
+ info->size = 0x100000;
+ for (i = 0; i < info->sector_count-4; i++) {
+ info->start[i] = base + i * 0x10000;
+ }
+ info->start[i] = base + i * 0x10000;
+ info->start[i+1] = base + i * 0x10000 + 0x8000;
+ info->start[i+2] = base + i * 0x10000 + 0xa000;
+ info->start[i+3] = base + i * 0x10000 + 0xc000;
+ }
+ else {
+ return 0;
+ }
+
+ /* mark all sectors as unprotected */
+ for (i = 0; i < info->sector_count; i++) {
+ info->protect[i] = 0;
+ }
+
+ /* Issue the reset command */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr[0] = 0xF0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_char *addr = (vu_char *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+ addr[0x0AAA] = 0x80;
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_char *)(info->start[sect]);
+ addr[0] = 0x30;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_char *)(info->start[l_sect]);
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ int rc;
+
+ while (cnt > 0) {
+ if ((rc = write_byte(info, addr, *src)) != 0) {
+ return (rc);
+ }
+ addr++;
+ src++;
+ cnt--;
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+ vu_char *addr = (vu_char *)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_char *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+ addr[0x0AAA] = 0xA0;
+
+ *((vu_char *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+
+int checkboard (void)
+{
+ puts ( "OXC8240\n" );
+ return 0;
+}
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+ int i, cnt;
+ volatile uchar * base= CFG_SDRAM_BASE;
+ volatile ulong * addr;
+ ulong save[32];
+ ulong val, ret = 0;
+
+ for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+ addr = (volatile ulong *)base + cnt;
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ addr = (volatile ulong *)base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if (*addr != 0) {
+ *addr = save[i];
+ goto Done;
+ }
+
+ for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+ addr = (volatile ulong *)base + cnt;
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt) {
+ ulong new_bank0_end = cnt * sizeof(long) - 1;
+ ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
+ ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ ret = cnt * sizeof(long);
+ goto Done;
+ }
+ }
+
+ ret = CFG_MAX_RAM_SIZE;
+Done:
+ return ret;
+#else
+ /* if PPCBoot starts from RAM, then suppose we have 16Mb of RAM */
+ return (16 << 20);
+#endif
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_oxc_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x14, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x15, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+ PCI_ENET1_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_oxc_config_table,
+#endif
+};
+
+void pci_init (bd_t * bd)
+{
+ pci_mpc824x_init(bd, &hose);
+}
+
+void board_pre_init(void)
+{
+ *(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89;
+}
+
+#ifdef CONFIG_WATCHDOG
+void oxc_wdt_reset(void)
+{
+ *(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff;
+}
+
+void watchdog_reset(void)
+{
+ int re_enable = disable_interrupts();
+
+ oxc_wdt_reset();
+ if (re_enable)
+ enable_interrupts();
+}
+#endif
+
+static int oxc_get_expander(unsigned char addr, unsigned char * val)
+{
+ return i2c_read(addr, 0, 0, val, 1);
+}
+
+static int oxc_set_expander(unsigned char addr, unsigned char val)
+{
+ return i2c_write(addr, 0, 0, &val, 1);
+}
+
+static int expander0alive = 0;
+
+#ifdef CONFIG_SHOW_ACTIVITY
+static int ledtoggle = 0;
+static int ledstatus = 1;
+
+void oxc_toggle_activeled(void)
+{
+ ledtoggle++;
+}
+
+void show_activity(int arg)
+{
+ static unsigned char led = 0;
+ unsigned char val;
+
+ if (!expander0alive) return;
+
+ if ((ledtoggle > (2 * arg)) && ledstatus) {
+ led ^= 0x80;
+ oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+ udelay(200);
+ oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led);
+ ledtoggle = 0;
+ }
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int arg)
+{
+ unsigned char val;
+
+ if (!expander0alive) return;
+
+ if (arg > 0 && ledstatus) {
+ ledstatus = 0;
+ oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+ udelay(200);
+ oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80);
+ } else if (arg < 0) {
+ oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+ udelay(200);
+ oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F);
+ ledstatus = 1;
+ }
+}
+#endif
+
+void misc_init_r(bd_t *bd)
+{
+ /* check whether the i2c expander #0 is accessible */
+ if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) {
+ udelay(200);
+ expander0alive = 1;
+ }
+
+#ifdef CFG_OXC_GENERATE_IP
+ {
+ char str[32];
+ unsigned long ip = CFG_OXC_IPMASK;
+
+ if (expander0alive) {
+ unsigned char val;
+
+ if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) {
+ ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2);
+ }
+ }
+
+ if ((ip & 0xff) < 3) {
+ /* if fail, set x.x.x.254 */
+ ip = (ip & 0xffffff00) | 0xfe;
+ }
+
+ bd->bi_ip_addr = ip;
+ sprintf(str, "%ld.%ld.%ld.%ld",
+ (bd->bi_ip_addr & 0xff000000) >> 24,
+ (bd->bi_ip_addr & 0x00ff0000) >> 16,
+ (bd->bi_ip_addr & 0x0000ff00) >> 8,
+ (bd->bi_ip_addr & 0x000000ff));
+ setenv("ipaddr", str);
+ printf("ip: %s\n", str);
+ }
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ common/board.o (.text)
+ ppc/ppcstring.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
+
static char *failed = "*** failed ***\n";
-#ifdef CONFIG_PCU_E
+#if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
extern flash_info_t flash_info[];
#endif
{
ulong *addr;
- addr = (ulong *)syscall_tbl;
syscall_tbl[SYSCALL_MALLOC] = (void *)malloc;
syscall_tbl[SYSCALL_FREE] = (void *)free;
*addr++ |= (ulong)syscall_tbl & 0xFFFF;
*addr++ |= NR_SYSCALLS >> 16;
*addr++ |= NR_SYSCALLS & 0xFFFF;
+
+ flush_cache(0xc00, 0x10);
}
/************************************************************************
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
#if defined(CONFIG_BOARD_PRE_INIT) || \
- defined(CONFIG_CU824) || \
- defined(CONFIG_EVB64260) || \
- defined(CONFIG_LWMON) || \
- defined(CONFIG_MPC8260ADS)|| \
- defined(CONFIG_RPXSUPER) || \
- defined(CONFIG_EP8260) || \
- defined(CONFIG_WALNUT405) || \
- defined(CONFIG_W7O)
+ defined(CONFIG_CU824) || \
+ defined(CONFIG_EP8260) || \
+ defined(CONFIG_EVB64260) || \
+ defined(CONFIG_LWMON) || \
+ defined(CONFIG_MPC8260ADS) || \
+ defined(CONFIG_OXC) || \
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_W7O) || \
+ defined(CONFIG_WALNUT405
board_pre_init(); /* very early board init code (fpga boot, etc.) */
#endif
bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
-#if defined(CONFIG_PCU_E)
+#if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
bd->bi_flashoffset = 0;
#elif CFG_MONITOR_BASE == CFG_FLASH_BASE
bd->bi_flashoffset = CFG_MONITOR_LEN; /* reserved area for startup monitor */
#elif defined(CONFIG_8260)
#include <asm/immap_8260.h>
#include <asm/cpm_8260.h>
+#include <asm/iopin_8260.h>
#endif
static void
-unimplemented(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+unimplemented (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- printf("Sorry, but the '%s' command has not been implemented\n",
- cmdtp->name);
+ printf ("Sorry, but the '%s' command has not been implemented\n",
+ cmdtp->name);
}
int
do_siuinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
#if defined(CONFIG_8xx)
- volatile sysconf8xx_t *sc = &immap->im_siu_conf;
+ volatile sysconf8xx_t *sc = &immap->im_siu_conf;
#elif defined(CONFIG_8260)
- volatile sysconf8260_t *sc = &immap->im_siu_conf;
+ volatile sysconf8260_t *sc = &immap->im_siu_conf;
#endif
- printf("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
+ printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
#if defined(CONFIG_8xx)
- printf("SWT = %08x\n", sc->sc_swt);
- printf("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
- printf("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
- printf("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
+ printf ("SWT = %08x\n", sc->sc_swt);
+ printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
+ printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
+ printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
#elif defined(CONFIG_8260)
- printf("BCR = %08x\n", sc->sc_bcr);
- printf("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
- sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
- printf("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n",
- sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl);
- printf("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2);
- printf("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2);
- printf("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem);
- printf("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem);
+ printf ("BCR = %08x\n", sc->sc_bcr);
+ printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
+ sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
+ printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n",
+ sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl);
+ printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2);
+ printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2);
+ printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem);
+ printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem);
#endif
- return 0;
+ return 0;
}
int
-do_memcinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+do_memcinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
#if defined(CONFIG_8xx)
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- int nbanks = 8;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ int nbanks = 8;
#elif defined(CONFIG_8260)
- volatile memctl8260_t *memctl = &immap->im_memctl;
- int nbanks = 12;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ int nbanks = 12;
#endif
- volatile uint *p = &memctl->memc_br0;
- int i;
-
- for (i = 0; i < nbanks; i++, p += 2)
- if (i < 10)
- printf("BR%d = %08x OR%d = %08x\n", i, p[0], i, p[1]);
- else
- printf("BR%d = %08x OR%d = %08x\n", i, p[0], i, p[1]);
-
- printf("MAR = %08x", memctl->memc_mar);
+ volatile uint *p = &memctl->memc_br0;
+ int i;
+
+ for (i = 0; i < nbanks; i++, p += 2) {
+ if (i < 10) {
+ printf ("BR%d = %08x OR%d = %08x\n",
+ i, p[0], i, p[1]);
+ } else {
+ printf ("BR%d = %08x OR%d = %08x\n",
+ i, p[0], i, p[1]);
+ }
+ }
+
+ printf ("MAR = %08x", memctl->memc_mar);
#if defined(CONFIG_8xx)
- printf(" MCR = %08x\n", memctl->memc_mcr);
+ printf (" MCR = %08x\n", memctl->memc_mcr);
#elif defined(CONFIG_8260)
- printf("\n");
+ printf ("\n");
#endif
- printf("MAMR = %08x MBMR = %08x",
- memctl->memc_mamr, memctl->memc_mbmr);
+ printf ("MAMR = %08x MBMR = %08x",
+ memctl->memc_mamr, memctl->memc_mbmr);
#if defined(CONFIG_8xx)
- printf("\nMSTAT = %04x\n", memctl->memc_mstat);
+ printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
#elif defined(CONFIG_8260)
- printf(" MCMR = %08x\n", memctl->memc_mcmr);
+ printf (" MCMR = %08x\n", memctl->memc_mcmr);
#endif
- printf("MPTPR = %04x MDR = %08x\n",
- memctl->memc_mptpr, memctl->memc_mdr);
+ printf ("MPTPR = %04x MDR = %08x\n",
+ memctl->memc_mptpr, memctl->memc_mdr);
#if defined(CONFIG_8260)
- printf("PSDMR = %08x LSDMR = %08x\n",
- memctl->memc_psdmr, memctl->memc_lsdmr);
- printf("PURT = %02x PSRT = %02x\n",
- memctl->memc_purt, memctl->memc_psrt);
- printf("LURT = %02x LSRT = %02x\n",
- memctl->memc_lurt, memctl->memc_lsrt);
- printf("IMMR = %08x\n", memctl->memc_immr);
+ printf ("PSDMR = %08x LSDMR = %08x\n",
+ memctl->memc_psdmr, memctl->memc_lsdmr);
+ printf ("PURT = %02x PSRT = %02x\n",
+ memctl->memc_purt, memctl->memc_psrt);
+ printf ("LURT = %02x LSRT = %02x\n",
+ memctl->memc_lurt, memctl->memc_lsrt);
+ printf ("IMMR = %08x\n", memctl->memc_immr);
#endif
- return 0;
+ return 0;
}
int
do_sitinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
#ifdef CONFIG_8260
int
-do_icinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+do_icinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
#endif
int
do_carinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
static int counter;
static void
header(void)
{
- char *data = "\
+ char *data = "\
-------------------------------- --------------------------------\
00000000001111111111222222222233 00000000001111111111222222222233\
01234567890123456789012345678901 01234567890123456789012345678901\
-------------------------------- --------------------------------\
";
- int i;
+ int i;
- if (counter % 2)
+ if (counter % 2)
putc('\n');
- counter = 0;
+ counter = 0;
- for (i = 0; i < 4; i++, data += 79)
- printf("%.79s\n", data);
+ for (i = 0; i < 4; i++, data += 79)
+ printf("%.79s\n", data);
}
-static void
-binary(char *label, uint value, int nbits)
+static void binary (char *label, uint value, int nbits)
{
- uint mask = 1 << (nbits - 1);
- int i, second = (counter++ % 2);
-
- if (second)
- putc(' ');
- puts(label);
- for (i = 32 + 1; i != nbits; i--)
- putc(' ');
-
- while (mask != 0) {
- if (value & mask)
- putc('1');
- else
- putc('0');
- mask >>= 1;
- }
-
- if (second)
- putc('\n');
+ uint mask = 1 << (nbits - 1);
+ int i, second = (counter++ % 2);
+
+ if (second)
+ putc (' ');
+ puts (label);
+ for (i = 32 + 1; i != nbits; i--)
+ putc (' ');
+
+ while (mask != 0) {
+ if (value & mask)
+ putc ('1');
+ else
+ putc ('0');
+ mask >>= 1;
+ }
+
+ if (second)
+ putc ('\n');
}
#if defined(CONFIG_8xx)
int
do_iopinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
#if defined(CONFIG_8xx)
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile ushort *l, *r;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile ushort *l, *r;
#elif defined(CONFIG_8260)
- volatile iop8260_t *iop = &immap->im_ioport;
- volatile uint *l, *r;
+ volatile iop8260_t *iop = &immap->im_ioport;
+ volatile uint *l, *r;
#endif
- volatile uint *R;
+ volatile uint *R;
- counter = 0;
- header();
+ counter = 0;
+ header ();
- /*
- * Ports A & B
- */
+ /*
+ * Ports A & B
+ */
#if defined(CONFIG_8xx)
- l = &iop->iop_padir;
- R = &immap->im_cpm.cp_pbdir;
+ l = &iop->iop_padir;
+ R = &immap->im_cpm.cp_pbdir;
#elif defined(CONFIG_8260)
- l = &iop->iop_pdira;
- R = &iop->iop_pdirb;
+ l = &iop->iop_pdira;
+ R = &iop->iop_pdirb;
#endif
- binary("PA_DIR", *l++, PA_NBITS); binary("PB_DIR", *R++, PB_NBITS);
- binary("PA_PAR", *l++, PA_NBITS); binary("PB_PAR", *R++, PB_NBITS);
+ binary ("PA_DIR", *l++, PA_NBITS);
+ binary ("PB_DIR", *R++, PB_NBITS);
+ binary ("PA_PAR", *l++, PA_NBITS);
+ binary ("PB_PAR", *R++, PB_NBITS);
#if defined(CONFIG_8260)
- binary("PA_SOR", *l++, PA_NBITS); binary("PB_SOR", *R++, PB_NBITS);
+ binary ("PA_SOR", *l++, PA_NBITS);
+ binary ("PB_SOR", *R++, PB_NBITS);
#endif
- binary("PA_ODR", *l++, PA_NB_ODR); binary("PB_ODR", *R++, PB_NB_ODR);
- binary("PA_DAT", *l++, PA_NBITS); binary("PB_DAT", *R++, PB_NBITS);
+ binary ("PA_ODR", *l++, PA_NB_ODR);
+ binary ("PB_ODR", *R++, PB_NB_ODR);
+ binary ("PA_DAT", *l++, PA_NBITS);
+ binary ("PB_DAT", *R++, PB_NBITS);
- header();
+ header ();
- /*
- * Ports C & D
- */
+ /*
+ * Ports C & D
+ */
#if defined(CONFIG_8xx)
- l = &iop->iop_pcdir;
- r = &iop->iop_pddir;
+ l = &iop->iop_pcdir;
+ r = &iop->iop_pddir;
#elif defined(CONFIG_8260)
- l = &iop->iop_pdirc;
- r = &iop->iop_pdird;
+ l = &iop->iop_pdirc;
+ r = &iop->iop_pdird;
#endif
- binary("PC_DIR", *l++, PC_NBITS); binary("PD_DIR", *r++, PD_NBITS);
- binary("PC_PAR", *l++, PC_NBITS); binary("PD_PAR", *r++, PD_NBITS);
+ binary ("PC_DIR", *l++, PC_NBITS);
+ binary ("PD_DIR", *r++, PD_NBITS);
+ binary ("PC_PAR", *l++, PC_NBITS);
+ binary ("PD_PAR", *r++, PD_NBITS);
#if defined(CONFIG_8xx)
- binary("PC_SO ", *l++, PC_NBITS); binary(" ", 0, 0); r++;
+ binary ("PC_SO ", *l++, PC_NBITS);
+ binary (" ", 0, 0);
+ r++;
#elif defined(CONFIG_8260)
- binary("PC_SOR", *l++, PC_NBITS); binary("PD_SOR", *r++, PD_NBITS);
- binary("PC_ODR", *l++, PC_NBITS); binary("PD_ODR", *r++, PD_NBITS);
+ binary ("PC_SOR", *l++, PC_NBITS);
+ binary ("PD_SOR", *r++, PD_NBITS);
+ binary ("PC_ODR", *l++, PC_NBITS);
+ binary ("PD_ODR", *r++, PD_NBITS);
#endif
- binary("PC_DAT", *l++, PC_NBITS); binary("PD_DAT", *r++, PD_NBITS);
+ binary ("PC_DAT", *l++, PC_NBITS);
+ binary ("PD_DAT", *r++, PD_NBITS);
#if defined(CONFIG_8xx)
- binary("PC_INT", *l++, PC_NBITS);
+ binary ("PC_INT", *l++, PC_NBITS);
#endif
- header();
- return 0;
+ header ();
+ return 0;
+}
+
+/*
+ * set the io pins
+ * this needs a clean up for smaller tighter code
+ * use *uint and set the address based on cmd + port
+ */
+int
+do_iopset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+#if defined(CONFIG_8260)
+ uint rcode = 0;
+ static uint port = 0;
+ static uint pin = 0;
+ static uint value = 0;
+ static enum { DIR, PAR, SOR, ODR, DAT } cmd = DAT;
+ iopin_t iopin;
+
+ if (argc != 5) {
+ printf ("iopset PORT PIN CMD VALUE\n");
+ return 1;
+ }
+ port = argv[1][0] - 'A';
+ if (port > 3)
+ port -= 0x20;
+ if (port > 3)
+ rcode = 1;
+ pin = simple_strtol (argv[2], NULL, 10);
+ if (pin > 31)
+ rcode = 1;
+
+
+ switch (argv[3][0]) {
+ case 'd':
+ if (argv[3][1] == 'a')
+ cmd = DAT;
+ else if (argv[3][1] == 'i')
+ cmd = DIR;
+ else
+ rcode = 1;
+ break;
+ case 'p':
+ cmd = PAR;
+ break;
+ case 'o':
+ cmd = ODR;
+ break;
+ case 's':
+ cmd = SOR;
+ break;
+ default:
+ printf ("iopset: unknown command %s\n", argv[3]);
+ rcode = 1;
+ }
+ if (argv[4][0] == '1')
+ value = 1;
+ else if (argv[4][0] == '0')
+ value = 0;
+ else
+ rcode = 1;
+ if (rcode == 0) {
+ iopin.port = port;
+ iopin.pin = pin;
+ switch (cmd) {
+ case DIR:
+ if (value)
+ iopin_set_out (&iopin);
+ else
+ iopin_set_in (&iopin);
+ break;
+ case PAR:
+ if (value)
+ iopin_set_ded (&iopin);
+ else
+ iopin_set_gen (&iopin);
+ break;
+ case SOR:
+ if (value)
+ iopin_set_opt2 (&iopin);
+ else
+ iopin_set_opt1 (&iopin);
+ break;
+ case ODR:
+ if (value)
+ iopin_set_odr (&iopin);
+ else
+ iopin_set_act (&iopin);
+ break;
+ case DAT:
+ if (value)
+ iopin_set_high (&iopin);
+ else
+ iopin_set_low (&iopin);
+ break;
+ }
+
+ }
+ return rcode;
+#else
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
+#endif
}
int
do_dmainfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
do_fccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
-static void
-prbrg(int n, uint val)
+static void prbrg (int n, uint val)
{
- uint extc = (val >> 14) & 3;
- uint cd = (val & CPM_BRG_CD_MASK) >> 1;
- uint div16 = (val & CPM_BRG_DIV16) != 0;
- /* Pointer to initial global data area */
- init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+ uint extc = (val >> 14) & 3;
+ uint cd = (val & CPM_BRG_CD_MASK) >> 1;
+ uint div16 = (val & CPM_BRG_DIV16) != 0;
+
+ /* Pointer to initial global data area */
+ init_data_t *idata =
+ (init_data_t *) (CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
#if defined(CONFIG_8xx)
- ulong clock = idata->cpu_clk;
+ ulong clock = idata->cpu_clk;
#elif defined(CONFIG_8260)
- ulong clock = idata->brg_clk;
+ ulong clock = idata->brg_clk;
#endif
- printf("BRG%d:", n);
+ printf ("BRG%d:", n);
- if (val & CPM_BRG_RST)
- puts(" RESET");
- else
- puts(" ");
+ if (val & CPM_BRG_RST)
+ puts (" RESET");
+ else
+ puts (" ");
- if (val & CPM_BRG_EN)
- puts(" ENABLED");
- else
- puts(" DISABLED");
+ if (val & CPM_BRG_EN)
+ puts (" ENABLED");
+ else
+ puts (" DISABLED");
- printf(" EXTC=%d", extc);
+ printf (" EXTC=%d", extc);
- if (val & CPM_BRG_ATB)
- puts(" ATB");
- else
- puts(" ");
+ if (val & CPM_BRG_ATB)
+ puts (" ATB");
+ else
+ puts (" ");
- printf(" DIVIDER=%4d", cd);
- if (extc == 0 && cd != 0) {
- uint baudrate;
+ printf (" DIVIDER=%4d", cd);
+ if (extc == 0 && cd != 0) {
+ uint baudrate;
- if (div16)
- baudrate = (clock / 16) / (cd + 1);
- else
- baudrate = clock / (cd + 1);
+ if (div16)
+ baudrate = (clock / 16) / (cd + 1);
+ else
+ baudrate = clock / (cd + 1);
- printf("=%6d bps", baudrate);
- }
- else
- puts(" ");
+ printf ("=%6d bps", baudrate);
+ } else {
+ puts (" ");
+ }
- if (val & CPM_BRG_DIV16)
- puts(" DIV16");
- else
- puts(" ");
+ if (val & CPM_BRG_DIV16)
+ puts (" DIV16");
+ else
+ puts (" ");
- putc('\n');
+ putc ('\n');
}
int
do_brginfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
#if defined(CONFIG_8xx)
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile uint *p = &cp->cp_brgc1;
+ volatile cpm8xx_t *cp = &immap->im_cpm;
+ volatile uint *p = &cp->cp_brgc1;
#elif defined(CONFIG_8260)
- volatile uint *p = &immap->im_brgc1;
+ volatile uint *p = &immap->im_brgc1;
#endif
- int i = 1;
+ int i = 1;
- while (i <= 4)
- prbrg(i++, *p++);
+ while (i <= 4)
+ prbrg (i++, *p++);
#if defined(CONFIG_8260)
- p = &immap->im_brgc5;
- while (i <= 8)
- prbrg(i++, *p++);
+ p = &immap->im_brgc5;
+ while (i <= 8)
+ prbrg (i++, *p++);
#endif
- return 0;
+ return 0;
}
int
do_i2cinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
#if defined(CONFIG_8xx)
- volatile i2c8xx_t *i2c = &immap->im_i2c;
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+ volatile i2c8xx_t *i2c = &immap->im_i2c;
+ volatile cpm8xx_t *cp = &immap->im_cpm;
+ volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
#elif defined(CONFIG_8260)
- volatile i2c8260_t *i2c = &immap->im_i2c;
- volatile iic_t *iip;
- uint dpaddr;
-
- dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
- if (dpaddr == 0)
- iip = NULL;
- else
- iip = (iic_t *)&immap->im_dprambase[dpaddr];
+ volatile i2c8260_t *i2c = &immap->im_i2c;
+ volatile iic_t *iip;
+ uint dpaddr;
+
+ dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE]));
+ if (dpaddr == 0)
+ iip = NULL;
+ else
+ iip = (iic_t *) & immap->im_dprambase[dpaddr];
#endif
- printf("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add);
- printf("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com);
- printf("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr);
-
- if (iip == NULL)
- printf("i2c parameter ram not allocated\n");
- else {
- printf("RBASE = %08x TBASE = %08x\n", iip->iic_rbase, iip->iic_tbase);
- printf("RFCR = %02x TFCR = %02x\n",
- iip->iic_rfcr, iip->iic_tfcr);
- printf("MRBLR = %04x\n", iip->iic_mrblr);
- printf("RSTATE= %08x RDP = %08x\n", iip->iic_rstate, iip->iic_rdp);
- printf("RBPTR = %04x RBC = %04x\n",
- iip->iic_rbptr, iip->iic_rbc);
- printf("RXTMP = %08x\n", iip->iic_rxtmp);
- printf("TSTATE= %08x TDP = %08x\n", iip->iic_tstate, iip->iic_tdp);
- printf("TBPTR = %04x TBC = %04x\n",
- iip->iic_tbptr, iip->iic_tbc);
- printf("TXTMP = %08x\n", iip->iic_txtmp);
- }
- return 0;
+ printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add);
+ printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com);
+ printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr);
+
+ if (iip == NULL)
+ printf ("i2c parameter ram not allocated\n");
+ else {
+ printf ("RBASE = %08x TBASE = %08x\n",
+ iip->iic_rbase, iip->iic_tbase);
+ printf ("RFCR = %02x TFCR = %02x\n",
+ iip->iic_rfcr, iip->iic_tfcr);
+ printf ("MRBLR = %04x\n", iip->iic_mrblr);
+ printf ("RSTATE= %08x RDP = %08x\n",
+ iip->iic_rstate, iip->iic_rdp);
+ printf ("RBPTR = %04x RBC = %04x\n",
+ iip->iic_rbptr, iip->iic_rbc);
+ printf ("RXTMP = %08x\n", iip->iic_rxtmp);
+ printf ("TSTATE= %08x TDP = %08x\n",
+ iip->iic_tstate, iip->iic_tdp);
+ printf ("TBPTR = %04x TBC = %04x\n",
+ iip->iic_tbptr, iip->iic_tbc);
+ printf ("TXTMP = %08x\n", iip->iic_txtmp);
+ }
+ return 0;
}
int
do_sccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
do_smcinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
do_spiinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
do_muxinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
-do_siinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+do_siinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
int
do_mccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- unimplemented(cmdtp, bd, flag, argc, argv);
- return 0;
+ unimplemented (cmdtp, bd, flag, argc, argv);
+ return 0;
}
-
#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */
CMD_TBL_IDE
CMD_TBL_IMINFO
CMD_TBL_IOPINFO
+ CMD_TBL_IOPSET
CMD_TBL_IRQINFO
CMD_TBL_JFFS2
CMD_TBL_KGDB
}
#endif
WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+
+#ifdef CONFIG_SHOW_ACTIVITY
+ while (!tstc()) {
+ extern void show_activity(int arg);
+ show_activity(0);
+ }
+#endif
c = getc();
/*
#if defined(CONFIG_SOFT_I2C)
-#undef DEBUG_I2C
+/* #define DEBUG_I2C */
/*-----------------------------------------------------------------------
(CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif
+#if defined(CFG_ASRISE) && defined(CFG_ASFALL)
+ CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
+ CFG_ASRISE << MCCR2_ASRISE_SHIFT |
+ CFG_ASFALL << MCCR2_ASFALL_SHIFT);
+#else
CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
+#endif
+
#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR3,
(((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
(CFG_BANK6_ENABLE << 6) |
(CFG_BANK7_ENABLE << 7));
-#ifdef CONFIG_MPC8245
+#ifdef CFG_PGMAX
CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
#endif
unsigned int temp;
I2C_STAT stat;
+ temp = load_runtime_reg (eumbbar, I2CSR);
+
#ifdef I2CDBG0
PRINT ("%s(%d): get stat = 0x%08x\n", __FILE__, __LINE__, temp);
#endif
- temp = load_runtime_reg (eumbbar, I2CSR);
stat.rsrv0 = (temp & 0xffffff00) >> 8;
stat.mcf = (temp & 0x00000080) >> 7;
stat.maas = (temp & 0x00000040) >> 6;
I2CStatus status;
uchar xaddr[4];
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
+ if (alen > 0) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
- status = I2C_do_buffer (0, I2C_MASTER_XMIT, chip, alen,
- &xaddr[4 - alen], I2C_NO_STOP, 1,
- I2C_NO_RESTART);
- if (status != I2C_SUCCESS) {
- PRINT ("i2c_read: can't send data address for read\n");
- return 1;
+ status = I2C_do_buffer (0, I2C_MASTER_XMIT, chip, alen,
+ &xaddr[4 - alen], I2C_NO_STOP, 1,
+ I2C_NO_RESTART);
+ if (status != I2C_SUCCESS) {
+ PRINT ("i2c_read: can't send data address for read\n");
+ return 1;
+ }
}
/* The data transfer will be a continuation. */
status = I2C_do_buffer (0, I2C_MASTER_RCV, chip, len,
- buffer, I2C_STOP, 1, I2C_RESTART);
+ buffer, I2C_STOP, 1, (alen > 0 ? I2C_RESTART :
+ I2C_NO_RESTART));
+
if (status != I2C_SUCCESS) {
PRINT ("i2c_read: can't perform data transfer\n");
return 1;
status = I2C_do_buffer (0, I2C_MASTER_XMIT, chip, alen + len,
dummy_buffer, I2C_STOP, 1, I2C_NO_RESTART);
+
if (status != I2C_SUCCESS) {
PRINT ("i2c_write: can't perform data transfer\n");
return 1;
set_dec (decrementer_count);
timestamp++;
+
+#if defined(CONFIG_WATCHDOG)
+ if ((timestamp % (CFG_HZ / 2)) == 0) {
+#if defined(CONFIG_OXC)
+ {
+ extern void oxc_wdt_reset (void);
+ oxc_wdt_reset();
+ }
+#endif
+ }
+#endif /* CONFIG_WATCHDOG */
+#if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)
+ if ((timestamp % (CFG_HZ / 10)) == 0) {
+ {
+ extern void oxc_toggle_activeled(void);
+ oxc_toggle_activeled();
+ }
+ }
+#endif
}
void reset_timer (void)
{
int i;
- int busfreq;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
fecp->fec_fun_code = 0x78000000;
/* Set MII speed to 2.5 MHz or slightly below.
- * This rounds up to a multiple of 5MHz so MII speed never
- * exceeds 2.5MHz for 48 MHz and other non-multiples of 5MHz.
+ * According to the MPC860T (Rev. D) Fast ethernet controller user
+ * manual (6.2.14),
+ * the MII management interface clock must be less than or equal
+ * to 2.5 MHz.
+ * This MDC frequency is equal to system clock / (2 * MII_SPEED).
+ * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
*/
- busfreq = (bd->bi_busfreq * 1000000 + 4999999) / 5000000;
- fecp->fec_mii_speed = ((busfreq * 1000000) / 2500000) & 0x7e;
+ fecp->fec_mii_speed = ((bd->bi_busfreq + 4999999) / 5000000) << 1;
#if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
/* Configure all of port D for MII.
--- /dev/null
+This document contains different information about the port
+of PPCBoot for the OXC board designed by Lucent Technologies,
+Inc.
+
+1. Showing activity
+
+PPCBoot for the OXC board can show its current status using
+the Active LED. This feature is configured by the following
+options:
+
+CONFIG_SHOW_ACTIVITY
+
+ When this option is on, the Active LED is blinking fast
+when PPCBoot runs in the idle loop (i.e. waits for user
+commands from serial console) and blinking slow when it
+downloads an image over network. When PPCBoot loads an image
+over serial line the Active LED does not blink and its state
+is random (i.e. either constant on or constant off).
+
+CONFIG_SHOW_BOOT_PROGRESS
+
+ When this option is on, PPCBoot switches the Active LED
+off before booting an image and switches it on if booting
+failed due to some reasons.
+
ias_cmd->status = 0;
ias_cmd->link = cpu_to_le32(phys_to_bus((u32) &tx_ring[tx_next]));
- memcpy(ias_cmd->params, bis->bi_enetaddr, 6);
+ memcpy(ias_cmd->params, dev->enetaddr, 6);
/* Tell the adapter where the TX ring is located.
*/
SREC += timer.srec
endif
+# Utility for resetting i82559 EEPROM
+ifeq ($(BOARD),oxc)
+SREC += eepro100_eeprom.srec
+endif
+
OBJS = $(SREC:.srec=.o)
LIB = libsyscall.a
--- /dev/null
+/*
+ Copyright 1998-2001 by Donald Becker.
+ This software may be used and distributed according to the terms of
+ the GNU General Public License (GPL), incorporated herein by reference.
+ Contact the author for use under other terms.
+
+ This program must be compiled with "-O"!
+ See the bottom of this file for the suggested compile-command.
+
+ The author may be reached as becker@scyld.com, or C/O
+ Scyld Computing Corporation
+ 410 Severn Ave., Suite 210
+ Annapolis MD 21403
+
+ Common-sense licensing statement: Using any portion of this program in
+ your own program means that you must give credit to the original author
+ and release the resulting code under the GPL.
+*/
+
+#include <ppcboot.h>
+#include <syscall.h>
+
+static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr);
+
+int eepro100_eeprom(void)
+{
+ int ret = 0;
+
+ unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 };
+ unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 };
+
+#if defined(CONFIG_OXC)
+ ret |= reset_eeprom(0x80000000, hwaddr1);
+ ret |= reset_eeprom(0x81000000, hwaddr2);
+#endif
+
+ return ret;
+}
+
+/* Default EEPROM for i82559 */
+static unsigned short default_eeprom[64] = {
+ 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
+};
+
+static unsigned short eeprom[256];
+
+static int eeprom_size = 64;
+static int eeprom_addr_size = 6;
+
+static int debug = 0;
+
+static inline unsigned short swap16(unsigned short x)
+{
+ return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
+}
+
+static inline void outw(short data, long addr)
+{
+ *(volatile short *)(addr) = swap16(data);
+}
+
+static inline short inw(long addr)
+{
+ return swap16(*(volatile short *)(addr));
+}
+
+static inline void *memcpy(void *dst, const void *src, unsigned int len)
+{
+ void * ret = dst;
+ while (len-- > 0) *((char *)dst)++ = *((char *)src)++;
+ return ret;
+}
+
+/* The EEPROM commands include the alway-set leading bit. */
+#define EE_WRITE_CMD (5)
+#define EE_READ_CMD (6)
+#define EE_ERASE_CMD (7)
+
+/* Serial EEPROM section. */
+#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
+#define EE_CS 0x02 /* EEPROM chip select. */
+#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
+#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
+#define EE_ENB (0x4800 | EE_CS)
+#define EE_WRITE_0 0x4802
+#define EE_WRITE_1 0x4806
+#define EE_OFFSET 14
+
+/* Delay between EEPROM clock transitions. */
+#define eeprom_delay(ee_addr) inw(ee_addr)
+
+/* Wait for the EEPROM to finish the previous operation. */
+static int eeprom_busy_poll(long ee_ioaddr)
+{
+ int i;
+ outw(EE_ENB, ee_ioaddr);
+ for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
+ if (inw(ee_ioaddr) & EE_DATA_READ)
+ break;
+ return i;
+}
+
+/* This executes a generic EEPROM command, typically a write or write enable.
+ It returns the data output from the EEPROM, and thus may also be used for
+ reads. */
+static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
+{
+ unsigned retval = 0;
+ long ee_addr = ioaddr + EE_OFFSET;
+
+ if (debug > 1)
+ mon_printf(" EEPROM op 0x%x: ", cmd);
+
+ outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
+
+ /* Shift the command bits out. */
+ do {
+ short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
+ outw(dataval, ee_addr);
+ eeprom_delay(ee_addr);
+ if (debug > 2)
+ mon_printf("%X", inw(ee_addr) & 15);
+ outw(dataval | EE_SHIFT_CLK, ee_addr);
+ eeprom_delay(ee_addr);
+ retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ } while (--cmd_len >= 0);
+#if 0
+ outw(EE_ENB, ee_addr);
+#endif
+ /* Terminate the EEPROM access. */
+ outw(EE_ENB & ~EE_CS, ee_addr);
+ if (debug > 1)
+ mon_printf(" EEPROM result is 0x%5.5x.\n", retval);
+ return retval;
+}
+
+static int read_eeprom(long ioaddr, int location, int addr_len)
+{
+ return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
+ << 16 , 3 + addr_len + 16) & 0xffff;
+}
+
+static void write_eeprom(long ioaddr, int index, int value, int addr_len)
+{
+ long ee_ioaddr = ioaddr + EE_OFFSET;
+ int i;
+
+ /* Poll for previous op finished. */
+ eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */
+ /* Enable programming modes. */
+ do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
+ /* Do the actual write. */
+ do_eeprom_cmd(ioaddr,
+ (((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
+ 3 + addr_len + 16);
+ /* Poll for write finished. */
+ i = eeprom_busy_poll(ee_ioaddr); /* Typical 2000 ticks */
+ if (debug)
+ mon_printf(" Write finished after %d ticks.\n", i);
+ /* Disable programming. This command is not instantaneous, so we check
+ for busy before the next op. */
+ do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
+ eeprom_busy_poll(ee_ioaddr);
+}
+
+static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
+{
+ unsigned short checksum = 0;
+ int size_test;
+ int i;
+
+ mon_printf("Resetting i82559 EEPROM @ 0x%08x ... ", ioaddr);
+
+ size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
+ eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
+ eeprom_size = 1 << eeprom_addr_size;
+
+ memcpy(eeprom, default_eeprom, sizeof default_eeprom);
+
+ for (i = 0; i < 3; i++)
+ eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
+
+ /* Recalculate the checksum. */
+ for (i = 0; i < eeprom_size - 1; i++)
+ checksum += eeprom[i];
+ eeprom[i] = 0xBABA - checksum;
+
+ for (i = 0; i < eeprom_size; i++)
+ write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
+
+ for (i = 0; i < eeprom_size; i++)
+ if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
+ mon_printf("failed\n");
+ return 1;
+ }
+
+ mon_printf("done\n");
+ return 0;
+}
+
),
#define CMD_TBL_IOPINFO MK_CMD_TBL_ENTRY( \
- "iopinfo", 3, 1, 1, do_iopinfo, \
+ "iopinfo", 4, 1, 1, do_iopinfo, \
"iopinfo - print I/O Port registers\n", \
NULL \
),
+#define CMD_TBL_IOPSET MK_CMD_TBL_ENTRY( \
+ "iopset", 4, 5, 0, do_iopset, \
+ "iopset - set I/O Port registers\n", \
+ "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" \
+),
+
#define CMD_TBL_DMAINFO MK_CMD_TBL_ENTRY( \
"dmainfo", 3, 1, 1, do_dmainfo, \
"dmainfo - print SDMA/IDMA registers\n", \
#endif
int do_carinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
int do_iopinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+int do_iopset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
int do_dmainfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
int do_fccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
int do_brginfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
#endif
#define CMD_TBL_CARINFO
#define CMD_TBL_IOPINFO
+#define CMD_TBL_IOPSET
#define CMD_TBL_DMAINFO
#define CMD_TBL_FCCINFO
#define CMD_TBL_BRGINFO
#undef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_IS_IN_NVRAM
+#define DEBUG_I2C
#undef CFG_ENV_IS_IN_EEPROM
#ifdef CFG_ENV_IS_IN_NVRAM
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8240 1
+#define CONFIG_OXC 1
+
+#define CONFIG_IDENT_STRING " [oxc] "
+
+#define CONFIG_WATCHDOG 1
+#define CONFIG_SHOW_ACTIVITY 1
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP 1 /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
+
+/*-----------------------------------------------------------------------
+ * Boot options
+ */
+
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_LOADADDR 0x10000
+#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf"
+#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000"
+#define CONFIG_BOOTDELAY 10
+
+#define CFG_OXC_GENERATE_IP 1 /* Generate IP automatically */
+#define CFG_OXC_IPMASK 0x0A000000 /* 10.0.0.x */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+
+#define CONFIG_PCI /* include pci support */
+
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
+
+#define PCI_ENET0_IOADDR 0x80000000
+#define PCI_ENET0_MEMADDR 0x80000000
+#define PCI_ENET1_IOADDR 0x81000000
+#define PCI_ENET1_MEMADDR 0x81000000
+
+/*-----------------------------------------------------------------------
+ * FLASH
+ */
+
+#define CFG_FLASH0_BASE 0xFFF00000
+#define CFG_FLASH1_BASE 0xFFE00000
+#define CFG_FLASH_BASE (0-flash_info[0].size)
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * RAM
+ */
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_MAX_RAM_SIZE 0x10000000
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN 0x00030000
+
+#if (CFG_MONITOR_BASE < CFG_FLASH0_BASE) && \
+ (CFG_MONITOR_BASE < CFG_FLASH1_BASE)
+# define CFG_RAMBOOT 1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+
+#define CFG_INIT_DATA_SIZE 128
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
+
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
+
+/*-----------------------------------------------------------------------
+ * Memory mapping
+ */
+
+#define CFG_CPLD_BASE 0xff000000 /* CPLD registers */
+#define CFG_CPLD_WATCHDOG (CFG_CPLD_BASE) /* Watchdog */
+#define CFG_CPLD_RESET (CFG_CPLD_BASE + 0x040000) /* Minor resets */
+#define CFG_UART_BASE (CFG_CPLD_BASE + 0x700000) /* debug UART */
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE -4
+#define CFG_NS16550_CLK 1843200
+#define CFG_NS16550_COM1 CFG_UART_BASE
+
+/*-----------------------------------------------------------------------
+ * I2C Bus
+ */
+
+#define CONFIG_I2C 1 /* I2C support on ... */
+#define CONFIG_HARD_I2C 1 /* ... hardware one */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+
+#define CFG_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */
+#define CFG_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */
+#define CFG_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
+
+#define CFG_EUMB_ADDR 0xFC000000
+
+/* MCCR1 */
+#define CFG_ROMNAL 0 /* rom/flash next access time */
+#define CFG_ROMFAL 19 /* rom/flash access time */
+
+/* MCCR2 */
+#define CFG_ASRISE 15 /* ASRISE=15 clocks */
+#define CFG_ASFALL 3 /* ASFALL=3 clocks */
+#define CFG_REFINT 1000 /* REFINT=1000 clocks */
+
+/* MCCR3 */
+#define CFG_BSTOPRE 0x35c /* Burst To Precharge */
+#define CFG_REFREC 7 /* Refresh to activate interval */
+#define CFG_RDLAT 4 /* data latency from read command */
+
+/* MCCR4 */
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_ACTORW 2 /* Activate to R/W */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x00000000
+#define CFG_BANK1_END 0x00000000
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x00000000
+#define CFG_BANK2_END 0x00000000
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x00000000
+#define CFG_BANK3_END 0x00000000
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x00000000
+#define CFG_BANK4_END 0x00000000
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x00000000
+#define CFG_BANK5_END 0x00000000
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x00000000
+#define CFG_BANK6_END 0x00000000
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x00000000
+#define CFG_BANK7_END 0x00000000
+#define CFG_BANK7_ENABLE 0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE 0x01
+
+#define CFG_ODCR 0xff /* configures line driver impedances, */
+ /* see 8240 book for bit definitions */
+#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
+ /* currently accessed page in memory */
+ /* see 8240 book for details */
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
+#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
+#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
+#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
struct NS16550 {
unsigned char rbr; /* 0 */
int pad1:24;
- unsigned long ier; /* 1 */
+ unsigned char ier; /* 1 */
int pad2:24;
- unsigned long fcr; /* 2 */
+ unsigned char fcr; /* 2 */
int pad3:24;
- unsigned long lcr; /* 3 */
+ unsigned char lcr; /* 3 */
int pad4:24;
- unsigned long mcr; /* 4 */
+ unsigned char mcr; /* 4 */
int pad5:24;
- unsigned long lsr; /* 5 */
+ unsigned char lsr; /* 5 */
int pad6:24;
- unsigned long msr; /* 6 */
+ unsigned char msr; /* 6 */
int pad7:24;
- unsigned long scr; /* 7 */
+ unsigned char scr; /* 7 */
int pad8:24;
} __attribute__ ((packed));
#else
*/
for (;;) {
WATCHDOG_RESET();
+#ifdef CONFIG_SHOW_ACTIVITY
+ {
+ extern void show_activity(int arg);
+ show_activity(1);
+ }
+#endif
/*
* Check the ethernet for a new packet. The ethernet
* receive routine will process it.
projects / users / rw / ppcboot.git / commitdiff