drm/amdgpu: avoid update aca bank multi times during ras isr

Because the UE Valid MCA count will only be cleared after reset,
in order to avoid repeated counting of the error count,
the aca bank is only updated once during ras isr.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 611c1751577a5e8ecb5385b3034ee7f784c1ab14..53ad76f590a1f55ee3f8a7f1adf21a55b76d3db0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -369,6 +369,26 @@ static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *
        return 0;
 }
 
+static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type)
+{
+       struct amdgpu_aca *aca = &adev->aca;
+       bool ret = true;
+
+       /*
+        * Because the UE Valid MCA count will only be cleared after reset,
+        * in order to avoid repeated counting of the error count,
+        * the aca bank is only updated once during the gpu recovery stage.
+        */
+       if (type == ACA_SMU_TYPE_UE) {
+               if (amdgpu_ras_intr_triggered())
+                       ret = atomic_cmpxchg(&aca->ue_update_flag, 0, 1) == 0;
+               else
+                       atomic_set(&aca->ue_update_flag, 0);
+       }
+
+       return ret;
+}
+
 static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,
                            bank_handler_t handler, void *data)
 {
@@ -380,6 +400,9 @@ static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,
        if (list_empty(&aca->mgr.list))
                return 0;
 
+       if (!aca_bank_should_update(adev, type))
+               return 0;
+
        ret = aca_smu_get_valid_aca_count(adev, type, &count);
        if (ret)
                return ret;
@@ -670,6 +693,8 @@ int amdgpu_aca_init(struct amdgpu_device *adev)
        struct amdgpu_aca *aca = &adev->aca;
        int ret;
 
+       atomic_set(&aca->ue_update_flag, 0);
+
        ret = aca_manager_init(&aca->mgr);
        if (ret)
                return ret;
@@ -682,6 +707,8 @@ void amdgpu_aca_fini(struct amdgpu_device *adev)
        struct amdgpu_aca *aca = &adev->aca;
 
        aca_manager_fini(&aca->mgr);
+
+       atomic_set(&aca->ue_update_flag, 0);
 }
 
 int amdgpu_aca_reset(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
index 6eb4c0341278fbb66dd2824acccc7f962183a1d1..674a5a9da8620a6261ba490adb6bfb1b156ba836 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h
@@ -175,6 +175,7 @@ struct aca_smu_funcs {
 struct amdgpu_aca {
        struct aca_handle_manager mgr;
        const struct aca_smu_funcs *smu_funcs;
+       atomic_t ue_update_flag;
        bool is_enabled;
 };