(and it uses default address).
======================================================================
-Modifications since 0.7.1:
+Modifications for 0.7.2:
======================================================================
+* New configuration for RDS prototype board (by Marius Gröger)
+
+* New i2c.c driver for 82xx (by Marius Gröger)
+
+* "setenv" and "saveenv" commands no longer auto-repeatable
+
+* Restrict baudrate settings to certain legal values (see table
+ CFG_BAUDRATE_TABLE in the board's config header file)
+
+* Now baudrate changes take place immediately (without reset)
+
----------------------------------------------------------------------
GENIETV patch by Paolo Scaffardi (Fri, 5 Jan 2001 11:27:44 +0100):
* Added support for AMDLV040B 512Kb flash into flash.h
[ -d LOG ] || mkdir LOG || exit 1
LIST=" \
- TQM823L TQM850L TQM855L TQM860L FPS850L SM850 \
- ETX094 SPD823TS IVMS8 \
- FADS823 FADS850SAR FADS860T MBX \
- CPCI405 ADCIOP \
- cogent_mpc8xx \
- GENIETV \
- SXNI855T \
- cogent_mpc8260 hymod \
- Sandpoint8240 \
- hermes IP860 \
+ TQM823L TQM850L TQM855L TQM860L FPS850L SM850 \
+ ETX094 SPD823TS IVMS8 \
+ FADS823 FADS850SAR FADS860T MBX \
+ CPCI405 ADCIOP \
+ cogent_mpc8xx \
+ GENIETV \
+ SXNI855T \
+ cogent_mpc8260 hymod \
+ Sandpoint8240 \
+ hermes IP860 \
+ rsdproto \
"
[ $# = 0 ] && set $LIST
echo "CPU = mpc8260" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+rsdproto_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = rsdproto" >>config.mk ; \
+ echo "CPU = mpc8260" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
#########################################################################
clean:
ppc/extable.o (.text)
ppc/zlib.o (.text)
+ common/cmd_boot.o (.text)
+ common/cmd_bootm.o (.text)
+ common/cmd_flash.o (.text)
+ common/cmd_mem.o (.text)
+ common/cmd_nvedit.o (.text)
+ common/console.o (.text)
+ common/lists.o (.text)
+ common/board.o (.text)
+ common/main.o (.text)
+
. = env_offset;
common/environment.o(.text)
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := rsdproto.o flash.o
+SOBJS :=
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+//TEXT_BASE = 0xfff00000
+TEXT_BASE = 0x00200000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+/* flash hardware ids */
+#define VENDOR_AMD 0x0001
+#define AMD_29DL323C_B 0x2253
+
+/* Define this to include autoselect sequence in flash_init(). Does NOT
+ * work when executing from flash itself, so this should be turned
+ * on only when debugging the RAM version.
+ */
+#undef WITH_AUTOSELECT
+
+#define ERR_OK 0
+#define ERR_TIMOUT 1
+#define ERR_NOT_ERASED 2
+#define ERR_PROTECTED 4
+#define ERR_INVAL 8
+#define ERR_ALIGN 16
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if 1
+#define D(x)
+#else
+#define D(x) printf x
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static unsigned char write_ull(flash_info_t *info, unsigned long address,
+ volatile unsigned long long data);
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+int flash_write(uchar *, ulong, ulong);
+flash_info_t *addr2info (ulong);
+
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+
+/*---------------------------------------------------------------------------
+*
+* MACRO NAME: ull_read/ull_write
+*
+* DESCRIPTION: uses the floating point unit from 8260 to read and write
+* 64 bit wide data (unsigned long long) on the 60x bus.
+* this is necessary because all 4 Flash Chips use the /WE line
+* from byte lane 0
+* important -> data should allways be 8-alligned, otherwise exception !!
+*
+* EXTERNAL EFFECT: scratch register f0
+*
+* PARAMETERS: 32 bit long pointer to adress, 64 bit long pointer to data
+*
+* RETURNS: nothing
+*--------------------------------------------------------------------------*/
+
+static void ull_write(unsigned long long volatile *address,
+ unsigned long long volatile *data)
+{
+ double tmp;
+
+ __asm__ __volatile__(
+ " lfd %0,0(%2)\n"
+ " stfd %1,0(%3)\n"
+ : "=f" (tmp) /* outputs */
+ : "0" (tmp), "r" (data), "r" (address) /* inputs */
+ );
+
+ D(("ull_write: address %08lx <- data %08lx%08lx\n",
+ (ulong)address,
+ (ulong)(*data >> 32), (ulong)(*data & 0xffffffff)));
+}
+
+#ifdef WITH_AUTOSELECT
+static void ull_read(unsigned long long *address,
+ unsigned long long *data)
+{
+ double tmp;
+
+ __asm__ __volatile__(
+ " lfd %0,0(%3)\n"
+ " stfd %1,0(%2)\n"
+ : "=f" (tmp) /* outputs */
+ : "0" (tmp), "r" (data), "r" (address) /* inputs */
+ );
+
+ D(("ull_read: address %08lx -> data %08lx%08lx\n",
+ (ulong)address,
+ (ulong)(*data >> 32), (ulong)(*data & 0xffffffff)));
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong addr;
+
+#ifdef WITH_AUTOSELECT
+ {
+ unsigned long long *f_addr = (unsigned long long *)CFG_FLASH_BASE;
+ unsigned long long f_command, vendor, device;
+ /* Perform Autoselect */
+ f_command = 0x00AA00AA00AA00AAULL;
+ ull_write(&f_addr[0x555], &f_command);
+ f_command = 0x0055005500550055ULL;
+ ull_write(&f_addr[0x2AA], &f_command);
+ f_command = 0x0090009000900090ULL;
+ ull_write(&f_addr[0x555], &f_command);
+ ull_read(&f_addr[0], &vendor);
+ vendor &= 0xffff;
+ ull_read(&f_addr[1], &device);
+ device &= 0xffff;
+ f_command = 0x00F000F000F000F0ULL;
+ ull_write(&f_addr[0x555], &f_command);
+ if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
+ return 0;
+ }
+#endif
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* 1st bank: 8 x 32 KB sectors */
+ flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+ flash_info[0].sector_count = 8;
+ flash_info[0].size = flash_info[0].sector_count * 32 * 1024;
+ addr = CFG_FLASH_BASE;
+ for(i = 0; i < flash_info[0].sector_count; i++) {
+ flash_info[0].start[i] = addr;
+ addr += flash_info[0].size / flash_info[0].sector_count;
+ }
+ /* 1st bank: 63 x 256 KB sectors */
+ flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+ flash_info[1].sector_count = 63;
+ flash_info[1].size = flash_info[1].sector_count * 256 * 1024;
+ for(i = 0; i < flash_info[1].sector_count; i++) {
+ flash_info[1].start[i] = addr;
+ addr += flash_info[1].size / flash_info[1].sector_count;
+ }
+
+ /*
+ * protect monitor and environment sectors
+ */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#if defined(CFG_FLASH_ENV_ADDR)
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_ENV_ADDR,
+#if defined(CFG_FLASH_ENV_BUF)
+ CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_BUF - 1,
+#else
+ CFG_FLASH_ENV_ADDR + CFG_ENV_SIZE - 1,
+#endif
+ &flash_info[0]);
+#endif
+
+ return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ * Check or set protection status for monitor sectors
+ *
+ * The monitor always occupies the _first_ part of the _first_ Flash bank.
+ */
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+ ulong b_end = info->start[0] + info->size - 1; /* bank end address */
+ int rc = 0;
+ int first = -1;
+ int last = -1;
+ int i;
+
+ if (to < info->start[0]) {
+ return (0);
+ }
+
+ for (i=0; i<info->sector_count; ++i) {
+ ulong end; /* last address in current sect */
+ short s_end;
+
+ s_end = info->sector_count - 1;
+
+ end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+ if (from > end) {
+ continue;
+ }
+ if (to < info->start[i]) {
+ continue;
+ }
+
+ if (from == info->start[i]) {
+ first = i;
+ if (last < 0) {
+ last = s_end;
+ }
+ }
+ if (to == end) {
+ last = i;
+ if (first < 0) {
+ first = 0;
+ }
+ }
+ }
+
+ for (i=first; i<=last; ++i) {
+ if (flag & FLAG_PROTECT_CLEAR) {
+ info->protect[i] = 0;
+ } else if (flag & FLAG_PROTECT_SET) {
+ info->protect[i] = 1;
+ }
+ if (info->protect[i]) {
+ rc = 1;
+ }
+ }
+ return (rc);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id >> 16) {
+ case VENDOR_AMD:
+ printf ("AMD ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case AMD_29DL323C_B:
+ printf ("AM29DL323CB (32 Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect, l_sect;
+ ulong start;
+ unsigned long long volatile *f_addr;
+ unsigned long long volatile f_command;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ f_addr = (unsigned long long *)info->start[0];
+ f_command = 0x00AA00AA00AA00AAULL;
+ ull_write(&f_addr[0x555], &f_command);
+ f_command = 0x0055005500550055ULL;
+ ull_write(&f_addr[0x2AA], &f_command);
+ f_command = 0x0080008000800080ULL;
+ ull_write(&f_addr[0x555], &f_command);
+ f_command = 0x00AA00AA00AA00AAULL;
+ ull_write(&f_addr[0x555], &f_command);
+ f_command = 0x0055005500550055ULL;
+ ull_write(&f_addr[0x2AA], &f_command);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+
+ f_addr =
+ (unsigned long long *)(info->start[sect]);
+ f_command = 0x0030003000300030ULL;
+ ull_write(f_addr, &f_command);
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+ do
+ {
+ if (get_timer(start) > CFG_FLASH_ERASE_TOUT)
+ { /* write reset command, command address is unimportant */
+ /* this command turns the flash back to read mode */
+ f_addr =
+ (unsigned long long *)(info->start[l_sect]);
+ f_command = 0x00F000F000F000F0ULL;
+ ull_write(f_addr, &f_command);
+ printf (" timeout\n");
+ return;
+ }
+ } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL);
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+ flash_info_t *info;
+ int i;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ info=&flash_info[i];
+ if ((addr >= info->start[0]) &&
+ (addr <= (info->start[0] + info->size - 1)) ) {
+ return info;
+ }
+ }
+
+ return NULL;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+ int i;
+ ulong end = addr + cnt - 1;
+ flash_info_t *info_first = addr2info (addr);
+ flash_info_t *info_last = addr2info (end );
+ flash_info_t *info;
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ if (!info_first || !info_last) {
+ return ERR_INVAL;
+ }
+
+ for (info = info_first; info <= info_last; ++info) {
+ ulong b_end = info->start[0] + info->size; /* bank end addr */
+ short s_end = info->sector_count - 1;
+ for (i=0; i<info->sector_count; ++i) {
+ ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+ if ((end >= info->start[i]) && (addr < e_addr) &&
+ (info->protect[i] != 0) ) {
+ return ERR_PROTECTED;
+ }
+ }
+ }
+
+ /* finally write data to flash */
+ for (info = info_first; info <= info_last && cnt>0; ++info) {
+ ulong len;
+
+ len = info->start[0] + info->size - addr;
+ if (len > cnt)
+ len = cnt;
+ if ((i = write_buff(info, src, addr, len)) != 0) {
+ return (i);
+ }
+ cnt -= len;
+ addr += len;
+ src += len;
+ }
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ unsigned long cp, wp;
+ unsigned long long data;
+ int i, l, rc;
+
+ wp = (addr & ~7); /* get lower long long aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<8 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<8; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_ull(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle long long aligned part
+ */
+ while (cnt >= 8) {
+ data = 0;
+ for (i=0; i<8; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_ull(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 8;
+ cnt -= 8;
+ }
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<8; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return write_ull(info, wp, data);
+}
+
+/*---------------------------------------------------------------------------
+*
+* FUNCTION NAME: write_ull
+*
+* DESCRIPTION: writes 8 bytes to flash
+*
+* EXTERNAL EFFECT: nothing
+*
+* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data
+*
+* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error
+*--------------------------------------------------------------------------*/
+
+static unsigned char write_ull(flash_info_t *info,
+ unsigned long address,
+ volatile unsigned long long data)
+{
+ static unsigned long long f_command;
+ static unsigned long long *f_addr;
+ ulong start;
+
+ /* address muss be 8-aligned! */
+ if (address & 0x7)
+ return ERR_ALIGN;
+
+ f_addr = (unsigned long long *)info->start[0];
+ f_command = 0x00AA00AA00AA00AAULL;
+ ull_write(&f_addr[0x555], &f_command);
+ f_command = 0x0055005500550055ULL;
+ ull_write(&f_addr[0x2AA], &f_command);
+ f_command = 0x00A000A000A000A0ULL;
+ ull_write(&f_addr[0x555], &f_command);
+
+ f_addr = (unsigned long long *)address;
+ f_command = data;
+ ull_write(f_addr, &f_command);
+
+ start = get_timer (0);
+ do
+ {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+ {
+ /* write reset command, command address is unimportant */
+ /* this command turns the flash back to read mode */
+ f_addr = (unsigned long long *)info->start[0];
+ f_command = 0x00F000F000F000F0ULL;
+ ull_write(f_addr, &f_command);
+ return ERR_TIMOUT;
+ }
+ } while(*((unsigned long long *)address) != data);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8260/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ . = env_offset;
+ common/environment.o(.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+
+/* define to initialise the SDRAM on the local bus */
+#undef INIT_LOCAL_BUS_SDRAM
+
+// I2C Bus adresses for PPC & Protocol board
+#define PPC8260_I2C_ADR 0x30 //(0)011.0000
+#define LM84_PPC_I2C_ADR 0x2A //(0)010.1010
+#define LM84_SHARC_I2C_ADR 0x29 //(0)010.1001
+#define VIRTEX_I2C_ADR 0x25 //(0)010.0101
+#define X24645_PPC_I2C_ADR 0x00 //(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!!
+#define RS5C372_PPC_I2C_ADR 0x32 //(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!!
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA30 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA29 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA28 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA27 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA26 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA25 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA24 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA23 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA21 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA20 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA19 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA18 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA17 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA16 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA15 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA14 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA13 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA12 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA11 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA10 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA9 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA8 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA7 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA6 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA5 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA4 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA3 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA2 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 },
+ /* PA0 */ { 0, 0, 0, 0, 0, 0 }
+ },
+
+
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 },
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC29 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC21 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC19 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */
+ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */
+ /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */
+ /* PC8 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 },
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }
+ },
+
+
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD28 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD27 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD26 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD25 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD24 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD23 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD22 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD21 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD20 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD19 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD18 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD17 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD16 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD9 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD8 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD7 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD6 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD5 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD4 */ { 0, 0, 0, 0, 0, 0 },
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+/* ------------------------------------------------------------------------- */
+
+struct tm {
+ unsigned int tm_sec;
+ unsigned int tm_min;
+ unsigned int tm_hour;
+ unsigned int tm_wday;
+ unsigned int tm_mday;
+ unsigned int tm_mon;
+ unsigned int tm_year;
+};
+
+const char bcd_table[2][8]={ { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
+ { 1, 2, 4, 8, 10, 20, 40, 80 }};
+
+unsigned char bcd2bin(unsigned char bcd_value)
+{
+ unsigned char n,bin_value=0;
+
+ for(n=0; n < 8 ; n++)
+ {
+ if(bcd_value & bcd_table[0][n])
+ bin_value += bcd_table[1][n];
+ }
+ return bin_value;
+}
+
+unsigned char bin2bcd(unsigned char bin_value)
+{
+ unsigned char n,bcd_value;
+
+ bcd_value = 0;
+
+ for(n = 7; n != 255 ; n--)
+ {
+ if(bin_value / bcd_table[1][n])
+ {
+ bcd_value += bcd_table[0][n];
+ bin_value -= bcd_table[1][n];
+ }
+ }
+ return bcd_value;
+}
+
+void read_RS5C372_time(struct tm *timedate)
+{
+ i2c_state_t i2c_state;
+ unsigned char buffer[8];
+ int rc;
+ int n;
+
+ i2c_newio(&i2c_state);
+
+ /* schedule send command with start condition */
+ rc = i2c_send(&i2c_state,
+ RS5C372_PPC_I2C_ADR, /* address */
+ 0x00, /* secondary address */
+ I2CF_ENABLE_SECONDARY | I2CF_START_COND,
+ 0, /* size */
+ NULL); /* data */
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ /* schedule the read command with repeated start condition */
+ rc = i2c_receive(&i2c_state,
+ RS5C372_PPC_I2C_ADR, /* address */
+ 0, /* secondary address */
+ I2CF_START_COND | I2CF_STOP_COND,
+ sizeof(buffer), /* size to expect */
+ buffer); /* data */
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ /* perform io operations */
+ rc = i2c_doio(&i2c_state);
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ for(n=0; n<7; n++)
+ buffer[n] = bcd2bin(buffer[n]);
+
+ timedate->tm_sec = buffer[0];
+ timedate->tm_min = buffer[1];
+ timedate->tm_hour = buffer[2];
+ timedate->tm_wday = buffer[3];
+ timedate->tm_mday = buffer[4];
+ timedate->tm_mon = buffer[5];
+ timedate->tm_year = buffer[6] + 2000;
+}
+
+/* ------------------------------------------------------------------------- */
+
+unsigned char read_LM84_temp(int address)
+{
+ i2c_state_t i2c_state;
+ unsigned char buffer[8];
+ int rc;
+
+ /* begin new i2c packet */
+ i2c_newio(&i2c_state);
+
+ /* schedule send operation */
+ rc = i2c_send(&i2c_state,
+ address, /* address */
+ 0x00, /* secondary address */
+ I2CF_ENABLE_SECONDARY | I2CF_START_COND | I2CF_STOP_COND,
+ 0, /* size */
+ NULL); /* data */
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ /* perform io operations */
+ rc = i2c_doio(&i2c_state);
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ /* begin new i2c packet */
+ i2c_newio(&i2c_state);
+
+ /* schedule send operation */
+ rc = i2c_receive(&i2c_state,
+ address, /* address */
+ 0, /* secondary address */
+ I2CF_START_COND | I2CF_STOP_COND,
+ 1, /* size to expect */
+ buffer); /* data */
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ /* perform io operations */
+ rc = i2c_doio(&i2c_state);
+ if (rc)
+ panic("i2c error %02x\n", rc);
+
+ return buffer[0];
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+ struct tm timedate;
+ unsigned char ppctemp, prottemp;
+
+ printf ("Rohde & Schwarz 8260 Protocol Board\n");
+
+ /* initialise i2c */
+ i2c_init(100000 >> 1, PPC8260_I2C_ADR);
+
+ read_RS5C372_time(&timedate);
+ printf(" Time: %02d:%02d:%02d\n", timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
+ printf(" Date: %02d-%02d-%04d\n", timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
+ ppctemp = read_LM84_temp(LM84_PPC_I2C_ADR);
+#if 0
+ /* can't read the LM84_SHARC_I2C_ADR ?! */
+ prottemp = read_LM84_temp(LM84_SHARC_I2C_ADR);
+#else
+ prottemp = 0;
+#endif
+ printf(" Temp: PPC %d C, Protocol Board %d C\n",
+ ppctemp, prottemp);
+
+ return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f(void)
+{
+ return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+#ifdef INIT_LOCAL_BUS_SDRAM
+ volatile uchar *ramaddr8;
+#endif
+ volatile ulong *ramaddr32;
+ ulong sdmr;
+ int i;
+
+ /*
+ * Only initialize SDRAM when running from FLASH.
+ * When running from RAM, don't touch it.
+ */
+ if ((ulong)initdram & 0xff000000)
+ {
+ immap->im_siu_conf.sc_ppc_acr = 0x02;
+ immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+ immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+ immap->im_siu_conf.sc_lcl_acr = 0x02;
+ immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+ immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+ /*
+ * Program local/60x bus Transfer Error Status and Control Regs:
+ * Disable parity errors
+ */
+ immap->im_siu_conf.sc_tescr1 = 0x00040000;
+ immap->im_siu_conf.sc_ltescr1 = 0x00040000;
+
+ /*
+ * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
+ *
+ * The appropriate BRx/ORx registers have already been set when we get
+ * here (see cpu_init_f). The SDRAM can be accessed at the address
+ * CFG_SDRAM_BASE.
+ */
+ memctl->memc_mptpr = 0x2000;
+ memctl->memc_mar = 0x0200;
+#ifdef INIT_LOCAL_BUS_SDRAM
+ /* initialise local bus ram
+ *
+ * (using the PSRMR_ definitions is NOT an error here - the LSDMR has
+ * the same fields as the PSDMR!)
+ */
+ memctl->memc_lsrt = 0x0b;
+ memctl->memc_lurt = 0x00;
+ ramaddr = (uchar*)PHYS_SDRAM_LOCAL;
+ sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+ memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
+ *ramaddr = 0xff;
+ for (i = 0; i < 8; i++)
+ {
+ memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
+ *ramaddr = 0xff;
+ }
+ memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
+ *ramaddr = 0xff;
+ memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+#endif
+ /* initialise 60x bus ram */
+ memctl->memc_psrt = 0x0b;
+ memctl->memc_purt = 0x08;
+ ramaddr32 = (ulong*)PHYS_SDRAM_60X;
+ sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+ memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
+ ramaddr32[0] = 0x00ff00ff;
+ ramaddr32[1] = 0x00ff00ff;
+ memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ {
+ ramaddr32[0] = 0x00ff00ff;
+ ramaddr32[1] = 0x00ff00ff;
+ }
+ memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
+ ramaddr32[0] = 0x00ff00ff;
+ ramaddr32[1] = 0x00ff00ff;
+ memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ }
+
+ /* return the size of the 60x bus ram */
+ return PHYS_SDRAM_60X_SIZE;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+void misc_init_r(bd_t *bd)
+{
+ printf("misc_init_r\n");
+}
#include <net.h>
#endif
+/*
+ * Table with supported baudrates (defined in config_xyz.h)
+ */
+static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE;
+#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
+
/************************************************************************
*
* The environment storages is simply a list of '\0'-terminated
static uchar *get_env_addr_memory(int index)
{
init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
-
+
if (idata->env_valid) {
return ( ((uchar *)(idata->env_addr + index)) );
} else {
return;
}
+ /*
+ * Switch to new baudrate if new baudrate is supported
+ */
+ if (strcmp(argv[1],"baudrate") == 0) {
+ int baudrate = simple_strtoul(argv[2], NULL, 10);
+ int i;
+ for (i=0; i<N_BAUDRATES; ++i) {
+ if (baudrate == baudrate_table[i])
+ break;
+ }
+ if (i == N_BAUDRATES) {
+ printf ("## Baudrate %d bps not supported\n",
+ baudrate);
+ return;
+ }
+ printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ baudrate);
+ udelay(50000);
+#if defined(CFG_CLKS_IN_HZ)
+ serial_setbrg (bd->bi_intfreq, baudrate);
+#else
+ serial_setbrg (bd->bi_intfreq * 1000000L, baudrate);
+#endif /* CFG_CLKS_IN_HZ */
+ udelay(50000);
+ for (;;) {
+ if (getc() == '\r')
+ break;
+ }
+ }
+
if (*++nxt == '\0') {
*env = '\0';
} else {
/* Update CRC */
env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
- /*
- * Some variables should be updated when the corresponding
+ /*
+ * Some variables should be updated when the corresponding
* entry in the enviornment is changed
*/
for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
int val, n;
-
+
for (nxt=i; get_env_char(nxt) != '\0'; ++nxt) {
if (nxt >= CFG_ENV_SIZE) {
return (-1);
idata->env_addr = 0;
idata->env_valid = 0;
}
-}
+}
#endif /* CFG_ENV_IS_IN_EEPROM */
START = start.o kgdb.o
OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
- interrupts.o ether_scc.o ether_fcc.o
+ interrupts.o ether_scc.o ether_fcc.o i2c.o
all: .depend $(START) $(LIB)
* Attention: this is board-specific
* - Rx-CLK is CLK14
* - Tx-CLK is CLK15
- * - RAM for BD/Buffers is on the Local Bus (see 28-13)
+ * - Select bus for bd/buffers (see 28-13)
* - Enable Full Duplex in FSMR
*/
#define CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CMXFCR_VALUE (CMXFCR_RF2CS_CLK14 | CMXFCR_TF2CS_CLK15)
-#define CPMFCR_RAMTYPE (CPMFCR_BDB | CPMFCR_DTB)
+#define CPMFCR_RAMTYPE (0)
#define FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+
+#ifdef CONFIG_I2C
+
+#include <asm/cpm_8260.h>
+#include <i2c.h>
+
+/* define to enable debug messages */
+#undef DEBUG_STEP
+
+/* us to wait before checking the i2c */
+#define DELAY_US 100000
+
+#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
+#define NUM_RX_BDS 4
+#define NUM_TX_BDS 4
+#define MAX_TX_SPACE 256
+
+typedef struct I2C_BD
+{
+ unsigned short status;
+ unsigned short length;
+ unsigned char *addr;
+} I2C_BD;
+#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
+
+#ifdef DEBUG_STEP
+#define PRINTD(x) printf x
+#else
+#define PRINTD(x)
+#endif
+
+/*
+ * Returns the best value of I2BRG to meet desired clock speed of I2C with
+ * input parameters (clock speed, filter, and predivider value).
+ * It returns computer speed value and the difference between it and desired
+ * speed.
+ */
+static inline int i2c_roundrate(int hz, int speed, int filter, int modval,
+ int *brgval, int *totspeed)
+{
+ int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
+
+ brgdiv = hz / (moddiv * speed);
+
+ *brgval = brgdiv / 2 - 3 - 2*filter;
+
+ if ((*brgval < 0) || (*brgval > 255))
+ return -1;
+
+ brgdiv = 2 * (*brgval + 3 + 2 * filter);
+ div = moddiv * brgdiv ;
+ *totspeed = hz / div;
+
+ return 0;
+}
+
+/*
+ * Sets the I2C clock predivider and divider to meet required clock speed.
+ */
+static int i2c_setrate(int hz, int speed)
+{
+ immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ int brgval,
+ modval, /* 0-3 */
+ bestspeed_diff = speed,
+ bestspeed_brgval=0,
+ bestspeed_modval=0,
+ bestspeed_filter=0,
+ totspeed,
+ filter = 0; /* Use this fixed value */
+
+ for (modval = 0; modval < 4; modval++)
+ {
+ if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
+ {
+ int diff = speed - totspeed ;
+
+ if ((diff >= 0) && (diff < bestspeed_diff))
+ {
+ bestspeed_diff = diff ;
+ bestspeed_modval = modval;
+ bestspeed_brgval = brgval;
+ bestspeed_filter = filter;
+ }
+ }
+ }
+
+ PRINTD(("[I2C] Best is:\n"));
+ PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
+ hz, speed,
+ bestspeed_filter, bestspeed_modval, bestspeed_brgval,
+ bestspeed_diff));
+
+ i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
+ i2c->i2c_i2brg = bestspeed_brgval & 0xff;
+
+ PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
+
+ return 1 ;
+}
+
+void i2c_init(int speed, int slaveaddr)
+{
+ init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ volatile iic_t *iip;
+ ulong rbase, tbase;
+ volatile I2C_BD *rxbd, *txbd;
+
+ /*
+ * initialise data in dual port ram:
+ *
+ * BD_IIC_START -> parameter ram (64 bytes)
+ * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
+ * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
+ * tx buffer (MAX_TX_SPACE bytes)
+ */
+
+ /* locate i2c parameter ram at BD_IIC_START */
+ iip = (iic_t *)&immap->im_dprambase[BD_IIC_START];
+ *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = BD_IIC_START;
+
+ memset((void*)iip, 0, sizeof(iic_t));
+
+ rbase = BD_IIC_START+64;
+ tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
+
+ /* Disable interrupts */
+ i2c->i2c_i2mod = 0x00;
+ i2c->i2c_i2cmr = 0x00;
+ i2c->i2c_i2cer = 0xff;
+ i2c->i2c_i2add = slaveaddr;
+
+ /*
+ * Set the I2C BRG Clock division factor from desired i2c rate
+ * and current CPU rate (we assume sccr dfbgr field is 0;
+ * divide BRGCLK by 1)
+ */
+ PRINTD(("[I2C] Setting rate...\n"));
+ i2c_setrate (idata->brg_clk, speed) ;
+
+ /* Set I2C controller in master mode */
+ i2c->i2c_i2com = 0x01;
+
+ /* Initialize Tx/Rx parameters */
+ iip->iic_rbase = rbase;
+ iip->iic_tbase = tbase;
+ rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
+ txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
+
+ PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
+ PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
+ PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+
+ /* Set big endian byte order */
+ iip->iic_tfcr = 0x10;
+ iip->iic_rfcr = 0x10;
+
+ /* Set maximum receive size. */
+ iip->iic_mrblr = I2C_RXTX_LEN;
+
+ cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
+ CPM_CR_I2C_SBLOCK,
+ 0x00,
+ CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ do {
+ __asm__ __volatile__ ("eieio");
+ } while (cp->cp_cpcr & CPM_CR_FLG);
+
+ /* Clear events and interrupts */
+ i2c->i2c_i2cer = 0xff;
+ i2c->i2c_i2cmr = 0x00;
+}
+
+void i2c_newio(i2c_state_t *state)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile iic_t *iip;
+
+ PRINTD(("[I2C] i2c_newio\n"));
+
+ iip = (iic_t *)&immap->im_dprambase[BD_IIC_START];
+ state->rx_idx = 0;
+ state->tx_idx = 0;
+ state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
+ state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
+ state->tx_space = MAX_TX_SPACE;
+ state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
+
+ PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
+ PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
+
+ /* clear the buffer memory */
+ memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
+}
+
+int i2c_send(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size,
+ unsigned char *dataout)
+{
+ volatile I2C_BD *txbd;
+ int i,j;
+
+ PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
+ address, secondary_address, flags, size));
+
+ /* trying to send message larger than BD */
+ if (size > I2C_RXTX_LEN)
+ return I2CERR_MSG_TOO_LONG;
+
+ /* no more free bds */
+ if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
+ return I2CERR_NO_BUFFERS;
+
+ txbd = (I2C_BD *)state->txbd;
+ txbd->addr = state->tx_buf;
+
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+
+ PRINTD(("[I2C] Formatting addresses...\n"));
+ if (flags & I2CF_ENABLE_SECONDARY)
+ {
+ txbd->length = size + 2; /* Length of message plus dest addresses */
+ txbd->addr[0] = address << 1;
+ txbd->addr[0] &= ~(0x01);
+ txbd->addr[1] = secondary_address;
+ i = 2;
+ }
+ else
+ {
+ txbd->length = size + 1; /* Length of message plus dest address */
+ txbd->addr[0] = address << 1; /* Write destination address to BD */
+ txbd->addr[0] &= ~(0x01); /* Set address to write */
+ i = 1;
+ }
+
+ /* set up txbd */
+ txbd->status = BD_SC_READY;
+ if (flags & I2CF_START_COND)
+ txbd->status |= BD_I2C_TX_START;
+ if (flags & I2CF_STOP_COND)
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+
+ /* Copy data to send into buffer */
+ PRINTD(("[I2C] copy data...\n"));
+ for(j = 0; j < size; i++, j++)
+ txbd->addr[i] = dataout[j];
+
+ PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]));
+
+ /* advance state */
+ state->tx_buf += txbd->length;
+ state->tx_space -= txbd->length;
+ state->tx_idx++;
+ state->txbd = (void*)(txbd + 1);
+
+ return 0;
+}
+
+int i2c_receive(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size_to_expect,
+ unsigned char *datain)
+{
+ volatile I2C_BD *rxbd, *txbd;
+
+ PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
+
+ /* Expected to receive too much */
+ if (size_to_expect > I2C_RXTX_LEN)
+ return I2CERR_MSG_TOO_LONG;
+
+ /* no more free bds */
+ if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
+ || state->tx_space < 2)
+ return I2CERR_NO_BUFFERS;
+
+ rxbd = (I2C_BD *)state->rxbd;
+ txbd = (I2C_BD *)state->txbd;
+
+ PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
+ PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+
+ txbd->addr = state->tx_buf;
+
+ /* set up TXBD for destination address */
+ if (flags & I2CF_ENABLE_SECONDARY)
+ {
+ txbd->length = 2;
+ txbd->addr[0] = address << 1; /* Write data */
+ txbd->addr[1] = secondary_address; /* Internal address */
+ txbd->status = BD_SC_READY;
+ }
+ else
+ {
+ txbd->length = 1 + size_to_expect;
+ txbd->addr[0] = (address << 1) | 0x01;
+ txbd->status = BD_SC_READY;
+ memset(&txbd->addr[1], 0, txbd->length);
+ }
+
+ /* set up rxbd for reception */
+ rxbd->status = BD_SC_EMPTY;
+ rxbd->length = size_to_expect;
+ rxbd->addr = datain;
+
+ if (flags & I2CF_START_COND)
+ txbd->status |= BD_I2C_TX_START;
+ if (flags & I2CF_STOP_COND)
+ {
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+ rxbd->status |= BD_SC_WRAP;
+ }
+
+ PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]));
+ PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ rxbd->length,
+ rxbd->status,
+ rxbd->addr[0],
+ rxbd->addr[1]));
+
+ /* advance state */
+ state->tx_buf += txbd->length;
+ state->tx_space -= txbd->length;
+ state->tx_idx++;
+ state->txbd = (void*)(txbd + 1);
+ state->rx_idx++;
+ state->rxbd = (void*)(rxbd + 1);
+
+ return 0;
+}
+
+
+int i2c_doio(i2c_state_t *state)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile iic_t *iip;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ volatile I2C_BD *txbd, *rxbd;
+
+ PRINTD(("[I2C] i2c_doio\n"));
+
+ txbd = ((I2C_BD*)state->txbd) - 1;
+ rxbd = ((I2C_BD*)state->rxbd) - 1;
+
+ iip = (iic_t *)&immap->im_dprambase[BD_IIC_START];
+ iip->iic_rbptr = iip->iic_rbase;
+ iip->iic_tbptr = iip->iic_tbase;
+
+ /* Enable I2C */
+ PRINTD(("[I2C] Enabling I2C...\n"));
+ i2c->i2c_i2mod |= 0x01;
+
+ /* Begin transmission */
+ i2c->i2c_i2com |= 0x80;
+
+ /* This is a patch! */
+ udelay (DELAY_US)
+ ;
+
+ /* Loop until transmit & receive completed */
+ PRINTD(("[I2C] Transmitting...\n"));
+ while(txbd->status & BD_SC_READY)
+ __asm__ __volatile__ ("eieio");
+
+ PRINTD(("[I2C] Receiving...\n"));
+ while(rxbd->status & BD_SC_EMPTY)
+ __asm__ __volatile__ ("eieio");
+
+ /* Turn off I2C */
+ i2c->i2c_i2mod &= ~0x01;
+
+ return 0;
+}
+
+
+#endif /* CONFIG_I2C */
volatile char val;
unsigned short br_reg;
- /*
- * Check for sanity
- */
- if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
- baudrate = CFG_BAUDRATE_DEFAULT;
br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16) / baudrate)-1);
/*
{
unsigned short br_reg;
- /*
- * Check for sanity
- */
- if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
- baudrate = CFG_BAUDRATE_DEFAULT;
br_reg = ((((CONFIG_CPUCLOCK * 1000000)/16) / baudrate)-1);
out8(SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); // Set baud rate divisor...
unsigned short br_reg;
unsigned long cntrl0Reg;
- /*
- * Check for sanity
- */
- if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
- baudrate = CFG_BAUDRATE_DEFAULT;
-
#ifdef CFG_EXT_SERIAL_CLOCK
/*
* Use external clock to generate serial clock
cntrl0Reg = mfdcr(cntrl0) & 0xffffe000;
cntrl0Reg |= 0x00001022;
mtdcr(cntrl0, cntrl0Reg); /* serial clock = cpu clock / 18 */
- br_reg = (((cpu_clock/16)/18) / baudrate);
+ br_reg = (((((cpu_clock/16)/18) * 10) / baudrate) + 5) / 10 ;
#endif
/*
{
unsigned short br_reg;
- /*
- * Check for sanity
- */
- if ((baudrate < CFG_BAUDRATE_MIN) || (baudrate > CFG_BAUDRATE_MAX))
- baudrate = CFG_BAUDRATE_DEFAULT;
#ifdef CFG_EXT_SERIAL_CLOCK
br_reg = ((CFG_EXT_SERIAL_CLOCK/16) / baudrate);
#else
- br_reg = (((cpu_clock/16)/18) / baudrate);
+ br_reg = (((((cpu_clock/16)/18) * 10) / baudrate) + 5) / 10 ;
#endif
out8(UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
#define CMD_TBL_SETENV MK_CMD_TBL_ENTRY( \
- "setenv", 6, CFG_MAXARGS, 1, do_setenv, \
+ "setenv", 6, CFG_MAXARGS, 0, do_setenv, \
"setenv - set environment variables\n", \
"name value ...\n" \
" - set environment variable 'name' to 'value ...'\n" \
#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
#define CMD_TBL_SAVEENV MK_CMD_TBL_ENTRY( \
- "saveenv", 4, 1, 1, do_saveenv, \
+ "saveenv", 4, 1, 0, do_saveenv, \
"saveenv - save environment variables to persistent storage\n", \
NULL \
),
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
-#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
-#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+
+#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
-#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
-#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
-#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
#if 1
-#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
+#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
#else
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
#endif
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
-#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
-#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
-#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#if 1
#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_IDE) & ~(CFG_CMD_ENV))
+ (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_IDE)
#else
#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ) & ~(CFG_CMD_ENV))
+ (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ)
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CFG_BAUDRATE_MIN 300 /* lowest possible baudrate */
-#define CFG_BAUDRATE_MAX 115200 /* highest possible baudrate */
-#define CFG_BAUDRATE_DEFAULT CONFIG_BAUDRATE /* default baudrate */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash*/
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the R&S Protocol Board board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
+#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on neither */
+#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
+#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
+#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
+
+/* enable I2C */
+#define CONFIG_I2C 1
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN 50000000 /* in Hz */
+
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 25 /* autoboot after 5 seconds */
+#endif
+//#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
+#define CONFIG_BOOTCOMMAND "bootp"
+
+#define CONFIG_BOOTARGS \
+ "root=/dev/nfs rw " \
+ "nfsroot=192.1.1.1:/LinuxPPC " \
+ "nfsaddrs=192.1.1.2:192.1.1.1:192.1.1.1:255.255.255.0:rsdproto::off"
+
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#undef CONFIG_WATCHDOG /* turn on platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
+#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
+
+#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
+#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_DPRAM_PCI 0x04000000 /* DPRAM PPC/PCI */
+#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
+
+#define PHYS_DPRAM_PCI_SEM 0x04020000 /* DPRAM PPC/PCI Semaphore */
+#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 /* 1 Byte */
+
+#define PHYS_DPRAM_SHARC 0x04100000 /* DPRAM PPC/Sharc */
+#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
+
+#define PHYS_DPRAM_SHARC_SEM 0x04140000 /* DPRAM PPC/Sharc Semaphore */
+#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 /* 1 Byte */
+
+#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
+#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
+
+#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
+
+#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+
+#define CFG_IMMR PHYS_IMMR
+
+/* turn off NVRAM env feature */
+#undef CONFIG_NVRAM_ENV
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#define CFG_HRCW_MASTER (HRCW_L2CPC10 | \
+ HRCW_DPPC11 | \
+ HRCW_ISB100 | \
+ HRCW_MMR00 | \
+ HRCW_APPC10 | \
+ HRCW_CS10PC00 | \
+ HRCW_MODCK_H0000)
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE PHYS_SDRAM_60X
+#define CFG_FLASH_BASE PHYS_FLASH
+#define CFG_MONITOR_BASE 0x200000
+//#define CFG_MONITOR_BASE 0xfff00000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CFG_HID2 0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR 0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR 0x100c0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
+ SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
+ SYPCR_SWRI | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR 0x00000000
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0
+
+/*
+ * Init Memory Controller:
+ */
+
+#define CFG_PSDMR 0x494D2452
+#define CFG_LSDMR 0x49492552
+
+#define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V)
+#define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
+ ORxG_BCTLD | \
+ ORxG_SCY_5_CLK)
+
+#define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
+#define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
+ ORxG_ACS_DIV4)
+
+#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
+#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
+ ORxS_BPD_4 | \
+ ORxS_ROWST_PBI1_A4 | \
+ ORxS_NUMR_13)
+
+#define CFG_BR3_PRELIM 0
+#define CFG_OR3_PRELIM 0
+
+#define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
+#define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
+ ORxS_BPD_4 | \
+ ORxS_ROWST_PBI1_A2 | \
+ ORxS_NUMR_13 | \
+ ORxS_IBID)
+
+#define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
+#define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
+ ORxG_ACS_DIV4)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#ifndef _I2C_H_
#define _I2C_H_
+#ifdef CONFIG_MPC8260
+
+/* This structure keeps track of the bd and buffer space usage. */
+typedef struct i2c_state {
+ int rx_idx, tx_idx; /* index to next free rx/tx bd */
+ void *rxbd, *txbd; /* pointer to next free rx/tx bd */
+ int tx_space; /* number of tx bytes left */
+ unsigned char *tx_buf; /* pointer to free tx area */
+} i2c_state_t;
+
+/* initialize i2c usage */
+void i2c_init(int speed, int slaveaddr);
+
+/* prepare a new io sequence */
+void i2c_newio(i2c_state_t *state);
+
+/* schedule a send operation (uses 1 tx bd) */
+int i2c_send(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size,
+ unsigned char *dataout);
+
+/* schedule a receive operation (uses 1 tx bd, 1 rx bd) */
+int i2c_receive(i2c_state_t *state,
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size_to_expect,
+ unsigned char *datain);
+
+/* execute all scheduled operations */
+int i2c_doio(i2c_state_t *state);
+
+/* flags for i2c_send() and i2c_receive() */
+#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
+#define I2CF_START_COND 0x02 /* tx: generate start condition */
+#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
+
+/* return codes */
+#define I2CERR_NO_BUFFERS 0x01 /* no more bds or buffer space */
+#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
+
+#else /* !CONFIG_MPC8260 */
+
void i2c_init(int speed);
void i2c_send( unsigned char address,
unsigned char secondary_address,
unsigned short size_to_expect, unsigned char datain[] );
#endif
+
+#endif
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.7.1"
+#define PPCBOOT_VERSION "ppcboot 0.7.2"
#endif /* __VERSION_H__ */
projects / users / rw / ppcboot.git / commitdiff