return 0;
 }
 
+static int amdgpu_ctx_query2(struct amdgpu_device *adev,
+       struct amdgpu_fpriv *fpriv, uint32_t id,
+       union drm_amdgpu_ctx_out *out)
+{
+       struct amdgpu_ctx *ctx;
+       struct amdgpu_ctx_mgr *mgr;
+
+       if (!fpriv)
+               return -EINVAL;
+
+       mgr = &fpriv->ctx_mgr;
+       mutex_lock(&mgr->lock);
+       ctx = idr_find(&mgr->ctx_handles, id);
+       if (!ctx) {
+               mutex_unlock(&mgr->lock);
+               return -EINVAL;
+       }
+
+       out->state.flags = 0x0;
+       out->state.hangs = 0x0;
+
+       if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter))
+               out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET;
+
+       if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
+               out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
+
+       if (atomic_read(&ctx->guilty))
+               out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
+
+       mutex_unlock(&mgr->lock);
+       return 0;
+}
+
 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
                     struct drm_file *filp)
 {
        case AMDGPU_CTX_OP_QUERY_STATE:
                r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
                break;
+       case AMDGPU_CTX_OP_QUERY_STATE2:
+               r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);
+               break;
        default:
                return -EINVAL;
        }
 
 #define AMDGPU_CTX_OP_ALLOC_CTX        1
 #define AMDGPU_CTX_OP_FREE_CTX 2
 #define AMDGPU_CTX_OP_QUERY_STATE      3
+#define AMDGPU_CTX_OP_QUERY_STATE2     4
 
 /* GPU reset status */
 #define AMDGPU_CTX_NO_RESET            0
 /* unknown cause */
 #define AMDGPU_CTX_UNKNOWN_RESET       3
 
+/* indicate gpu reset occured after ctx created */
+#define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
+/* indicate vram lost occured after ctx created */
+#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
+/* indicate some job from this context once cause gpu hang */
+#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
+
 /* Context priority level */
 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023