arm64: dts: exynosautov920: add CPU cache information

Add CPU caches information to its dt nodes so that the same is
available to userspace via sysfs. This SoC has 64/64 KB I/D cache and
256KB of L2 cache for each core, 2 MB of shared L3 cache for each quad
cpu cluster and 1 MB of shared L3 cache for the dual cpu cluster.

Signed-off-by: Devang Tailor <dev.tailor@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250108055012.1938530-1-dev.tailor@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index eb446cdc4ab69c27a239b2514e1b370317c2d4e3..a3fd503c1b2123f5ce08192952e20e42ab374dda 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -89,6 +89,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl0>;
                };
 
                cpu1: cpu@100 {
@@ -96,6 +103,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl0>;
                };
 
                cpu2: cpu@200 {
@@ -103,6 +117,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x200>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl0>;
                };
 
                cpu3: cpu@300 {
@@ -110,6 +131,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x300>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl0>;
                };
 
                cpu4: cpu@10000 {
@@ -117,6 +145,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x10000>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl1>;
                };
 
                cpu5: cpu@10100 {
@@ -124,6 +159,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x10100>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl1>;
                };
 
                cpu6: cpu@10200 {
@@ -131,6 +173,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x10200>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl1>;
                };
 
                cpu7: cpu@10300 {
@@ -138,6 +187,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x10300>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl1>;
                };
 
                cpu8: cpu@20000 {
@@ -145,6 +201,13 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x20000>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl2>;
                };
 
                cpu9: cpu@20100 {
@@ -152,6 +215,70 @@
                        compatible = "arm,cortex-a78ae";
                        reg = <0x0 0x20100>;
                        enable-method = "psci";
+                       i-cache-size = <0x10000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x10000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_cache_cl2>;
+               };
+
+               l2_cache_cl0: l2-cache0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x40000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+                       next-level-cache = <&l3_cache_cl0>;
+               };
+
+               l2_cache_cl1: l2-cache1 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x40000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+                       next-level-cache = <&l3_cache_cl1>;
+               };
+
+               l2_cache_cl2: l2-cache2 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x40000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+                       next-level-cache = <&l3_cache_cl2>;
+               };
+
+               l3_cache_cl0: l3-cache0 {
+                       compatible = "cache";
+                       cache-level = <3>;
+                       cache-unified;
+                       cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
+                       cache-line-size = <64>;
+                       cache-sets = <2048>;
+               };
+
+               l3_cache_cl1: l3-cache1 {
+                       compatible = "cache";
+                       cache-level = <3>;
+                       cache-unified;
+                       cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
+                       cache-line-size = <64>;
+                       cache-sets = <2048>;
+               };
+
+               l3_cache_cl2: l3-cache2 {
+                       compatible = "cache";
+                       cache-level = <3>;
+                       cache-unified;
+                       cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
+                       cache-line-size = <64>;
+                       cache-sets = <1365>;
                };
        };