clk: meson: mpll: Delete a useless spinlock from the MPLL

The register corresponding to MPLL does not share the same register
with other module drivers, so there is no concurrent access to the
register with other modules drivers. The spinlock defined in struct
meson_clk_mpll_data is no longer useful.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240925-mpll_spinlock-v2-1-8f9b73588ec1@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 757c7a28c53de65a5b662466d28910c350ed27d9..1b08daf579b2e57c4f618ce13d10206330fdce3e 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -23,8 +23,6 @@
 
 #include <dt-bindings/clock/axg-clkc.h>
 
-static DEFINE_SPINLOCK(meson_clk_lock);
-
 static struct clk_regmap axg_fixed_pll_dco = {
        .data = &(struct meson_clk_pll_data){
                .en = {
@@ -506,7 +504,6 @@ static struct clk_regmap axg_mpll0_div = {
                        .shift   = 0,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
        },
        .hw.init = &(struct clk_init_data){
@@ -557,7 +554,6 @@ static struct clk_regmap axg_mpll1_div = {
                        .shift   = 1,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
        },
        .hw.init = &(struct clk_init_data){
@@ -613,7 +609,6 @@ static struct clk_regmap axg_mpll2_div = {
                        .shift   = 2,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
        },
        .hw.init = &(struct clk_init_data){
@@ -664,7 +659,6 @@ static struct clk_regmap axg_mpll3_div = {
                        .shift   = 3,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
        },
        .hw.init = &(struct clk_init_data){

diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index f639d56f0fd3f3e4fe99d0f10d328dd71f938576..aa9abd06ae653585f68043bb1ddc2b0b96feeb6d 100644 (file)
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -112,26 +112,15 @@ static int mpll_set_rate(struct clk_hw *hw,
        struct clk_regmap *clk = to_clk_regmap(hw);
        struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
        unsigned int sdm, n2;
-       unsigned long flags = 0;
 
        params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
 
-       if (mpll->lock)
-               spin_lock_irqsave(mpll->lock, flags);
-       else
-               __acquire(mpll->lock);
-
        /* Set the fractional part */
        meson_parm_write(clk->map, &mpll->sdm, sdm);
 
        /* Set the integer divider part */
        meson_parm_write(clk->map, &mpll->n2, n2);
 
-       if (mpll->lock)
-               spin_unlock_irqrestore(mpll->lock, flags);
-       else
-               __release(mpll->lock);
-
        return 0;
 }
 

diff --git a/drivers/clk/meson/clk-mpll.h b/drivers/clk/meson/clk-mpll.h
index a991d568c43ae0ab36f2e42c08227e259b8eae1b..4ffd3aeef79952398ba8eb812e625e060e8b12a2 100644 (file)
--- a/drivers/clk/meson/clk-mpll.h
+++ b/drivers/clk/meson/clk-mpll.h
@@ -20,7 +20,6 @@ struct meson_clk_mpll_data {
        struct parm misc;
        const struct reg_sequence *init_regs;
        unsigned int init_count;
-       spinlock_t *lock;
        u8 flags;
 };
 

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 02dda57105b10ee89106c893dc767bf689b7b323..d3539fe9f7af5538201a78ce560f662ddb3935f2 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -28,8 +28,6 @@
 
 #include <dt-bindings/clock/g12a-clkc.h>
 
-static DEFINE_SPINLOCK(meson_clk_lock);
-
 static struct clk_regmap g12a_fixed_pll_dco = {
        .data = &(struct meson_clk_pll_data){
                .en = {
@@ -2225,7 +2223,6 @@ static struct clk_regmap g12a_mpll0_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = g12a_mpll0_init_regs,
                .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
        },
@@ -2279,7 +2276,6 @@ static struct clk_regmap g12a_mpll1_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = g12a_mpll1_init_regs,
                .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
        },
@@ -2333,7 +2329,6 @@ static struct clk_regmap g12a_mpll2_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = g12a_mpll2_init_regs,
                .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
        },
@@ -2387,7 +2382,6 @@ static struct clk_regmap g12a_mpll3_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = g12a_mpll3_init_regs,
                .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
        },

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index f071faad1ebb701a3c2c453bc82c0ca855685918..262c318edbd512239b79e5ad26643ae6c7b0173b 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -19,8 +19,6 @@
 
 #include <dt-bindings/clock/gxbb-clkc.h>
 
-static DEFINE_SPINLOCK(meson_clk_lock);
-
 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
        PLL_PARAMS(32, 1),
        PLL_PARAMS(33, 1),
@@ -731,7 +729,6 @@ static struct clk_regmap gxbb_mpll0_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
@@ -760,7 +757,6 @@ static struct clk_regmap gxl_mpll0_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
@@ -812,7 +808,6 @@ static struct clk_regmap gxbb_mpll1_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll1_div",
@@ -855,7 +850,6 @@ static struct clk_regmap gxbb_mpll2_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll2_div",

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index b7417ac262d33ed96f690b731a769a2cc06d34a5..5011768c0f4e04904a91947aba2029af188f1e3b 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -492,7 +492,6 @@ static struct clk_regmap meson8b_mpll0_div = {
                        .shift   = 25,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
@@ -537,7 +536,6 @@ static struct clk_regmap meson8b_mpll1_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll1_div",
@@ -582,7 +580,6 @@ static struct clk_regmap meson8b_mpll2_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .lock = &meson_clk_lock,
        },
        .hw.init = &(struct clk_init_data){
                .name = "mpll2_div",

diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
index 9697f6577e061baf29e5bd84fa93d7c2ea96cdab..d8e621e794281a14cdbc90e1990f677a087771ef 100644 (file)
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
@@ -17,8 +17,6 @@
 #include "meson-clkc-utils.h"
 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
 
-static DEFINE_SPINLOCK(meson_clk_lock);
-
 /*
  * These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
  * The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
@@ -547,7 +545,6 @@ static struct clk_regmap s4_mpll0_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = s4_mpll0_init_regs,
                .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
        },
@@ -601,7 +598,6 @@ static struct clk_regmap s4_mpll1_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = s4_mpll1_init_regs,
                .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
        },
@@ -655,7 +651,6 @@ static struct clk_regmap s4_mpll2_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = s4_mpll2_init_regs,
                .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
        },
@@ -709,7 +704,6 @@ static struct clk_regmap s4_mpll3_div = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .lock = &meson_clk_lock,
                .init_regs = s4_mpll3_init_regs,
                .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
        },