return ret;
 }
+
+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,
+                                       int nps_mode)
+{
+       /* Not supported on VF devices and APUs */
+       if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
+               return -EOPNOTSUPP;
+
+       if (!adev->psp.funcs) {
+               dev_err(adev->dev,
+                       "PSP interface not available for nps mode change request");
+               return -EINVAL;
+       }
+
+       return psp_memory_partition(&adev->psp, nps_mode);
+}
 
 
        enum amdgpu_memory_partition (*query_mem_partition_mode)(
                struct amdgpu_device *adev);
+       /* Request NPS mode */
+       int (*request_mem_partition_mode)(struct amdgpu_device *adev,
+                                         int nps_mode);
 };
 
 struct amdgpu_xgmi_ras {
        struct amdgpu_mem_partition_info *mem_partitions;
        uint8_t num_mem_partitions;
        const struct amdgpu_gmc_funcs   *gmc_funcs;
+       enum amdgpu_memory_partition    requested_nps_mode;
 
        struct amdgpu_xgmi xgmi;
        struct amdgpu_irq_src   ecc_irq;
                                 struct amdgpu_mem_partition_info *mem_ranges,
                                 int exp_ranges);
 
+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,
+                                       int nps_mode);
 #endif
 
        task_barrier_init(&hive->tb);
        hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
        hive->hi_req_gpu = NULL;
+       atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE);
 
        /*
         * hive pstate on boot is high in vega20 so we have to go to low
 
        atomic_t ras_recovery;
        struct ras_event_manager event_mgr;
        struct work_struct reset_on_init_work;
+       atomic_t requested_nps_mode;
 };
 
 struct amdgpu_pcs_ras_field {