if (cmd->data)
                cmd_reg |= MMCCMD_WDATX;
 
-       /* Setting whether stream or block transfer */
-       if (cmd->flags & MMC_DATA_STREAM)
-               cmd_reg |= MMCCMD_STRMTP;
-
        /* Setting whether data read or write */
        if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
                cmd_reg |= MMCCMD_DTRW;
                return;
        }
 
-       dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n",
-               (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
+       dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
                (data->flags & MMC_DATA_WRITE) ? "write" : "read",
                data->blocks, data->blksz);
        dev_dbg(mmc_dev(host->mmc), "  DTO %d cycles + %d ns\n",
        writel(data->blksz, host->base + DAVINCI_MMCBLEN);
 
        /* Configure the FIFO */
-       switch (data->flags & MMC_DATA_WRITE) {
-       case MMC_DATA_WRITE:
+       if (data->flags & MMC_DATA_WRITE) {
                host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
                writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
                        host->base + DAVINCI_MMCFIFOCTL);
                writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
                        host->base + DAVINCI_MMCFIFOCTL);
-               break;
-
-       default:
+       } else {
                host->data_dir = DAVINCI_MMC_DATADIR_READ;
                writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
                        host->base + DAVINCI_MMCFIFOCTL);
                writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
                        host->base + DAVINCI_MMCFIFOCTL);
-               break;
        }
 
        host->buffer = NULL;