clk: renesas: rzv2h: Add support for RZ/G3E SoC

The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.

Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ff01f5f0ed207afcea615b361d095e5d55a2cb91..5a4bc3f94d49a4cd22a9d12987e1918be3eca472 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -40,6 +40,7 @@ config CLK_RENESAS
        select CLK_R9A07G054 if ARCH_R9A07G054
        select CLK_R9A08G045 if ARCH_R9A08G045
        select CLK_R9A09G011 if ARCH_R9A09G011
+       select CLK_R9A09G047 if ARCH_R9A09G047
        select CLK_R9A09G057 if ARCH_R9A09G057
        select CLK_SH73A0 if ARCH_SH73A0
 
@@ -194,6 +195,10 @@ config CLK_R9A09G011
        bool "RZ/V2M clock support" if COMPILE_TEST
        select CLK_RZG2L
 
+config CLK_R9A09G047
+       bool "RZ/G3E clock support" if COMPILE_TEST
+       select CLK_RZV2H
+
 config CLK_R9A09G057
        bool "RZ/V2H(P) clock support" if COMPILE_TEST
        select CLK_RZV2H
@@ -234,7 +239,7 @@ config CLK_RZG2L
        select RESET_CONTROLLER
 
 config CLK_RZV2H
-       bool "RZ/V2H(P) family clock support" if COMPILE_TEST
+       bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
        select RESET_CONTROLLER
 
 config CLK_RENESAS_VBATTB

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 82efaa835ac70f47918308dae7c8b6f833b51679..2d6e746939c405a3c548319f059956fbb6ad4831 100644 (file)
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044)           += r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A07G054)            += r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)            += r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)            += r9a09g011-cpg.o
+obj-$(CONFIG_CLK_R9A09G047)            += r9a09g047-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)            += r9a09g057-cpg.o
 obj-$(CONFIG_CLK_SH73A0)               += clk-sh73a0.o
 

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
new file mode 100644 (file)
index 0000000..1178335
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E CPG driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum clk_ids {
+       /* Core Clock Outputs exported to DT */
+       LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
+
+       /* External Input Clocks */
+       CLK_AUDIO_EXTAL,
+       CLK_RTXIN,
+       CLK_QEXTAL,
+
+       /* PLL Clocks */
+       CLK_PLLCM33,
+       CLK_PLLDTY,
+       CLK_PLLCA55,
+
+       /* Internal Core Clocks */
+       CLK_PLLCM33_DIV16,
+       CLK_PLLDTY_ACPU,
+       CLK_PLLDTY_ACPU_DIV4,
+
+       /* Module Clocks */
+       MOD_CLK_BASE,
+};
+
+static const struct clk_div_table dtable_2_64[] = {
+       {0, 2},
+       {1, 4},
+       {2, 8},
+       {3, 16},
+       {4, 64},
+       {0, 0},
+};
+
+static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
+       /* External Clock Inputs */
+       DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
+       DEF_INPUT("rtxin", CLK_RTXIN),
+       DEF_INPUT("qextal", CLK_QEXTAL),
+
+       /* PLL Clocks */
+       DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+       DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
+       DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
+
+       /* Internal Core Clocks */
+       DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+       DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+       DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
+       /* Core Clocks */
+       DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+};
+
+static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
+       DEF_MOD_CRITICAL("gic_0_gicclk",        CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
+                                               BUS_MSTOP(3, BIT(5))),
+       DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
+                                               BUS_MSTOP(3, BIT(14))),
+};
+
+static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
+       DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
+       DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
+       DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */
+       DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+};
+
+const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
+       /* Core Clocks */
+       .core_clks = r9a09g047_core_clks,
+       .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
+       .last_dt_core_clk = LAST_DT_CORE_CLK,
+       .num_total_core_clks = MOD_CLK_BASE,
+
+       /* Module Clocks */
+       .mod_clks = r9a09g047_mod_clks,
+       .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
+       .num_hw_mod_clks = 28 * 16,
+
+       /* Resets */
+       .resets = r9a09g047_resets,
+       .num_resets = ARRAY_SIZE(r9a09g047_resets),
+
+       .num_mstop_bits = 208,
+};

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index d4fd52b0a24e93588b579668c1031f33207ddf00..a4c1e92e1fd7653035e5e4557138672674101333 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -972,6 +972,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
                .compatible = "renesas,r9a09g057-cpg",
                .data = &r9a09g057_cpg_info,
        },
+#endif
+#ifdef CONFIG_CLK_R9A09G047
+       {
+               .compatible = "renesas,r9a09g047-cpg",
+               .data = &r9a09g047_cpg_info,
+       },
 #endif
        { /* sentinel */ }
 };

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index dcd65e9c09da4c683349811c2c5c90e344a22afc..fd8eb985c75b29b2a80a4f6e8ffd28037fd72577 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -218,6 +218,7 @@ struct rzv2h_cpg_info {
        unsigned int num_mstop_bits;
 };
 
+extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
 extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
 
 #endif /* __RENESAS_RZV2H_CPG_H__ */