KPLL_CON0, NULL),
 };
 
+static const struct samsung_cmu_info cmu __initconst = {
+       .pll_clks       = exynos5410_plls,
+       .nr_pll_clks    = ARRAY_SIZE(exynos5410_plls),
+       .mux_clks       = exynos5410_mux_clks,
+       .nr_mux_clks    = ARRAY_SIZE(exynos5410_mux_clks),
+       .div_clks       = exynos5410_div_clks,
+       .nr_div_clks    = ARRAY_SIZE(exynos5410_div_clks),
+       .gate_clks      = exynos5410_gate_clks,
+       .nr_gate_clks   = ARRAY_SIZE(exynos5410_gate_clks),
+       .nr_clk_ids     = CLK_NR_CLKS,
+};
+
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
-       struct samsung_clk_provider *ctx;
-       void __iomem *reg_base;
-
-       reg_base = of_iomap(np, 0);
-       if (!reg_base)
-               panic("%s: failed to map registers\n", __func__);
-
-       ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
-
-       samsung_clk_register_pll(ctx, exynos5410_plls,
-                       ARRAY_SIZE(exynos5410_plls), reg_base);
-
-       samsung_clk_register_mux(ctx, exynos5410_mux_clks,
-                       ARRAY_SIZE(exynos5410_mux_clks));
-       samsung_clk_register_div(ctx, exynos5410_div_clks,
-                       ARRAY_SIZE(exynos5410_div_clks));
-       samsung_clk_register_gate(ctx, exynos5410_gate_clks,
-                       ARRAY_SIZE(exynos5410_gate_clks));
-
-       samsung_clk_of_add_provider(np, ctx);
+       samsung_cmu_register_one(np, &cmu);
 
        pr_debug("Exynos5410: clock setup completed.\n");
 }