"jedec,ufs-2.0";
                        reg = <0 0x01d84000 0 0x3000>;
                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
-                       phys = <&ufs_mem_phy_lanes>;
+                       phys = <&ufs_mem_phy>;
                        phy-names = "ufsphy";
                        lanes-per-direction = <2>;
                        #reset-cells = <1>;
 
                ufs_mem_phy: phy@1d87000 {
                        compatible = "qcom,sm8250-qmp-ufs-phy";
-                       reg = <0 0x01d87000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01d87000 0 0x1000>;
+
                        clock-names = "ref",
                                      "ref_aux";
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
 
                        resets = <&ufs_mem_hc 0>;
                        reset-names = "ufsphy";
-                       status = "disabled";
 
-                       ufs_mem_phy_lanes: phy@1d87400 {
-                               reg = <0 0x01d87400 0 0x16c>,
-                                     <0 0x01d87600 0 0x200>,
-                                     <0 0x01d87c00 0 0x200>,
-                                     <0 0x01d87800 0 0x16c>,
-                                     <0 0x01d87a00 0 0x200>;
-                               #phy-cells = <0>;
-                       };
+                       #phy-cells = <0>;
+
+                       status = "disabled";
                };
 
                cryptobam: dma-controller@1dc4000 {