arm64: dts: ti: k3-j784s4-evm: Use 4 lanes for PCIe0 on EVM

The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4
lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM
via SERDES1. Since SERDES1 is not being used by any peripheral apart
from PCIe0, use all 4 lanes of SERDES1 for PCIe0.

Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240720110455.3043327-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index ffa38f41679d8436f570682dc6133c53f51bbef3..ea27519d7b89d2eef4cd94bcc3758e6f77b28c48 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1407,10 +1407,11 @@
 
        serdes1_pcie0_link: phy@0 {
                reg = <0>;
-               cdns,num-lanes = <2>;
+               cdns,num-lanes = <4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
-               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>,
+                        <&serdes_wiz1 3>, <&serdes_wiz1 4>;
        };
 };