void __init time_init(void)
 {
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
 static int __init customize_machine(void)
 
 #ifdef CONFIG_COMMON_CLK
                of_clk_init(NULL);
 #endif
-               clocksource_probe();
+               timer_probe();
        }
 }
 
        }
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 };
 
 static const char * const mediatek_board_dt_compat[] = {
 
        __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
                        2, "timer_sys_ck", NULL, false);
 
-       clocksource_probe();
+       timer_probe();
 }
 
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
        __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
                        2, "timer_sys_ck", NULL, false);
 
-       clocksource_probe();
+       timer_probe();
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
        __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
                        1, "timer_sys_ck", "ti,timer-alwon", true);
        if (of_have_populated_dt())
-               clocksource_probe();
+               timer_probe();
 }
 #endif
 
 void __init omap4_local_timer_init(void)
 {
        omap4_sync32k_timer_init();
-       clocksource_probe();
+       timer_probe();
 }
 #endif
 
        omap4_sync32k_timer_init();
        realtime_counter_init();
 
-       clocksource_probe();
+       timer_probe();
 }
 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 
 
        }
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
 static void __init rockchip_dt_init(void)
 
 #endif /* CONFIG_ARM_ARCH_TIMER */
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
 struct memory_reserve_config {
 
        clk_put(pclk);
 
        spear_setup_of_timer();
-       clocksource_probe();
+       timer_probe();
 }
 
        of_clk_init(NULL);
        if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
                sun6i_reset_init();
-       clocksource_probe();
+       timer_probe();
 }
 
 DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
 
 DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
        .map_io         = u300_map_io,
        .init_irq       = u300_init_irq_dt,
-       .init_time      = clocksource_probe,
+       .init_time      = timer_probe,
        .init_machine   = u300_init_machine_dt,
        .restart        = u300_restart,
        .dt_compat      = u300_board_compat,
 
 {
        zynq_clock_init();
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
 static struct map_desc zynq_cortex_a9_scu_map __initdata = {
 
        u32 arch_timer_rate;
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 
        tick_setup_hrtimer_broadcast();
 
 
 void __init time_init(void)
 {
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
 {
        of_clk_init(NULL);
        setup_cpuinfo_clk();
-       clocksource_probe();
+       timer_probe();
 }
 
 #ifdef CONFIG_DEBUG_FS
 
                }
        }
 
-       clocksource_probe();
+       timer_probe();
 }
 
 void __init arch_init_irq(void)
 
                       (freq%1000000)*100/1000000);
 #ifdef CONFIG_CLKSRC_MIPS_GIC
                update_gic_frequency_dt();
-               clocksource_probe();
+               timer_probe();
 #endif
        }
 #endif
 
        pr_info("CPU Clock: %ldMHz\n", rate / 1000000);
        mips_hpt_frequency = rate / 2;
 
-       clocksource_probe();
+       timer_probe();
 }
 
        struct clk *clk;
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 
        np = of_get_cpu_node(0, NULL);
        if (!np) {
 
        pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
        mips_hpt_frequency = clk_get_rate(clk) / 2;
        clk_put(clk);
-       clocksource_probe();
+       timer_probe();
 }
 
        ralink_of_remap();
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 }
 
        struct clk *clk;
 
        of_clk_init(NULL);
-       clocksource_probe();
+       timer_probe();
 
        np = of_get_cpu_node(0, NULL);
        if (!np) {
 
        if (count < 2)
                panic("%d timer is found, it needs 2 timers in system\n", count);
 
-       clocksource_probe();
+       timer_probe();
 }
 
 TIMER_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);
 
 static void __init sh_of_time_init(void)
 {
        pr_info("SH generic board support: scanning for clocksource devices\n");
-       clocksource_probe();
+       timer_probe();
 }
 
 static void __init sh_of_setup(char **cmdline_p)
 
        local_timer_setup(0);
        setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);
        sched_clock_register(ccount_sched_clock_read, 32, ccount_freq);
-       clocksource_probe();
+       timer_probe();
 }
 
 /*
 
 static const struct of_device_id __clksrc_of_table_sentinel
        __used __section(__clksrc_of_table_end);
 
-void __init clocksource_probe(void)
+void __init timer_probe(void)
 {
        struct device_node *np;
        const struct of_device_id *match;
 
        OF_DECLARE_1_RET(clksrc, name, compat, fn)
 
 #ifdef CONFIG_CLKSRC_PROBE
-extern void clocksource_probe(void);
+extern void timer_probe(void);
 #else
-static inline void clocksource_probe(void) {}
+static inline void timer_probe(void) {}
 #endif
 
 #define CLOCKSOURCE_ACPI_DECLARE(name, table_id, fn)           \