clk: renesas: r8a779g0: Add SASYNCPER clocks

On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or
Fractional Multiplication to reduce electromagnetic interference.

Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock
sources for modules that must not be affected by Spread Spectrum and/or
Fractional Multiplication.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 9641122133b54f9aa0cf18adefdf3bfd25db98ea..3e8c93facfa14df4ccb755663a270a660f9852ef 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -47,6 +47,7 @@ enum clk_ids {
        CLK_S0_VIO,
        CLK_S0_VC,
        CLK_S0_HSC,
+       CLK_SASYNCPER,
        CLK_SV_VIP,
        CLK_SV_IR,
        CLK_SDSRC,
@@ -84,6 +85,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED(".s0_vio",    CLK_S0_VIO,     CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED(".s0_vc",     CLK_S0_VC,      CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED(".s0_hsc",    CLK_S0_HSC,     CLK_PLL1_DIV2,  2, 1),
+       DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
        DEF_FIXED(".sv_vip",    CLK_SV_VIP,     CLK_PLL1,       5, 1),
        DEF_FIXED(".sv_ir",     CLK_SV_IR,      CLK_PLL1,       5, 1),
        DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
@@ -128,6 +130,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("s0d4_hsc",   R8A779G0_CLK_S0D4_HSC,  CLK_S0_HSC,     4, 1),
        DEF_FIXED("cl16m_hsc",  R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC,     48, 1),
        DEF_FIXED("s0d2_cc",    R8A779G0_CLK_S0D2_CC,   CLK_S0,         2, 1),
+       DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+       DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+       DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
        DEF_FIXED("svd1_ir",    R8A779G0_CLK_SVD1_IR,   CLK_SV_IR,      1, 1),
        DEF_FIXED("svd2_ir",    R8A779G0_CLK_SVD2_IR,   CLK_SV_IR,      2, 1),
        DEF_FIXED("svd1_vip",   R8A779G0_CLK_SVD1_VIP,  CLK_SV_VIP,     1, 1),