drm/i915/adl_p: Allow underrun recovery when possible

ADL_P requires that we disable underrun recovery when downscaling (or
using the scaler for YUV420 pipe output), using DSC, or using PSR2.
Otherwise we should be able to enable the underrun recovery.

On DG2 we need to keep underrun recovery disabled at all times, but the
chicken bit in PIPE_CHICKEN has an inverted meaning (it's an enable bit
instead of disable).

v2:
 - Reverse the condition (clear the disable bit when supported, set
   disable bit when not supported).

Bspec: 50351
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210727145056.2049720-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 34a961143efcf1cdb903de0e9ab0b72ca962146e..456cb384317fefcb96fc8aff9c01d92f244921d8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2208,8 +2208,26 @@ unlock:
        clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
 }
 
-static void icl_set_pipe_chicken(struct intel_crtc *crtc)
+static bool underrun_recovery_supported(const struct intel_crtc_state *crtc_state)
 {
+       if (crtc_state->pch_pfit.enabled &&
+           (crtc_state->pipe_src_w > drm_rect_width(&crtc_state->pch_pfit.dst) ||
+            crtc_state->pipe_src_h > drm_rect_height(&crtc_state->pch_pfit.dst) ||
+            crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420))
+               return false;
+
+       if (crtc_state->dsc.compression_enable)
+               return false;
+
+       if (crtc_state->has_psr2)
+               return false;
+
+       return true;
+}
+
+static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        u32 tmp;
@@ -2230,19 +2248,19 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
         */
        tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 
-       /*
-        * "The underrun recovery mechanism should be disabled
-        *  when the following is enabled for this pipe:
-        *  WiDi
-        *  Downscaling (this includes YUV420 fullblend)
-        *  COG
-        *  DSC
-        *  PSR2"
-        *
-        * FIXME: enable whenever possible...
-        */
-       if (IS_ALDERLAKE_P(dev_priv))
-               tmp |= UNDERRUN_RECOVERY_DISABLE;
+       if (IS_DG2(dev_priv)) {
+               /*
+                * Underrun recovery must always be disabled on DG2.  However
+                * the chicken bit meaning is inverted compared to other
+                * platforms.
+                */
+               tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
+       } else if (DISPLAY_VER(dev_priv) >= 13) {
+               if (underrun_recovery_supported(crtc_state))
+                       tmp &= ~UNDERRUN_RECOVERY_DISABLE_ADLP;
+               else
+                       tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
+       }
 
        intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 }
@@ -3580,7 +3598,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
        hsw_set_linetime_wm(new_crtc_state);
 
        if (DISPLAY_VER(dev_priv) >= 11)
-               icl_set_pipe_chicken(crtc);
+               icl_set_pipe_chicken(new_crtc_state);
 
        if (dev_priv->display.initial_watermarks)
                dev_priv->display.initial_watermarks(state, crtc);
@@ -10212,7 +10230,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
                hsw_set_linetime_wm(new_crtc_state);
 
        if (DISPLAY_VER(dev_priv) >= 11)
-               icl_set_pipe_chicken(crtc);
+               icl_set_pipe_chicken(new_crtc_state);
 }
 
 static void commit_pipe_pre_planes(struct intel_atomic_state *state,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4d0ad70d04c488f4606de601d72b44064610789..730afa341f8a40882ed9638c2224081003fbdfad 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8393,7 +8393,8 @@ enum {
 #define _PIPEC_CHICKEN                         0x72038
 #define PIPE_CHICKEN(pipe)                     _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
                                                           _PIPEB_CHICKEN)
-#define   UNDERRUN_RECOVERY_DISABLE            REG_BIT(30)
+#define   UNDERRUN_RECOVERY_DISABLE_ADLP       REG_BIT(30)
+#define   UNDERRUN_RECOVERY_ENABLE_DG2         REG_BIT(30)
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU     (1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN            (1 << 7)