arm64: dts: ti: k3-j784s4-evm: Reserve memory for remote proc IPC

Reserve memory for remote processors. Two memory regions are reserved
for each remote processor. The first 1Mb region is used for virtio
Vring buffers for IPC and the second region is used for holding
resource table, trace buffer and as external memory to the remote
processor. The mailboxes are also assigned for each remote processor.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index f33815953e7792b9d4e9962966bcf5eb665ad995..1200cc677eb692f4bf254dbd3e483e9c2526956a 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -42,6 +42,150 @@
                        reg = <0x00 0x9e800000 0x00 0x01800000>;
                        no-map;
                };
+
+               mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa8000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_0_memory_region: c71-memory@a8100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa8100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_1_dma_memory_region: c71-dma-memory@a9000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa9000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_1_memory_region: c71-memory@a9100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa9100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_2_dma_memory_region: c71-dma-memory@aa000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xaa000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_2_memory_region: c71-memory@aa100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xaa100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_3_dma_memory_region: c71-dma-memory@ab000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xab000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_3_memory_region: c71-memory@ab100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xab100000 0x00 0xf00000>;
+                       no-map;
+               };
        };
 
        evm_12v0: regulator-evm12v0 {
@@ -253,3 +397,177 @@
        phy-mode = "rgmii-rxid";
        phy-handle = <&mcu_phy0>;
 };
+
+&mailbox0_cluster0 {
+       status = "okay";
+       interrupts = <436>;
+
+       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster1 {
+       status = "okay";
+       interrupts = <432>;
+
+       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster2 {
+       status = "okay";
+       interrupts = <428>;
+
+       mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster3 {
+       status = "okay";
+       interrupts = <424>;
+
+       mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster4 {
+       status = "okay";
+       interrupts = <420>;
+
+       mbox_c71_0: mbox-c71-0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_c71_1: mbox-c71-1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster5 {
+       status = "okay";
+       interrupts = <416>;
+
+       mbox_c71_2: mbox-c71-2 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_c71_3: mbox-c71-3 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mcu_r5fss0_core0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+                       <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+                       <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       memory-region = <&main_r5fss0_core0_dma_memory_region>,
+                       <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       memory-region = <&main_r5fss0_core1_dma_memory_region>,
+                       <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+       memory-region = <&main_r5fss1_core0_dma_memory_region>,
+                       <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+       memory-region = <&main_r5fss1_core1_dma_memory_region>,
+                       <&main_r5fss1_core1_memory_region>;
+};
+
+&main_r5fss2_core0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
+       memory-region = <&main_r5fss2_core0_dma_memory_region>,
+                       <&main_r5fss2_core0_memory_region>;
+};
+
+&main_r5fss2_core1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
+       memory-region = <&main_r5fss2_core1_dma_memory_region>,
+                       <&main_r5fss2_core1_memory_region>;
+};
+
+&c71_0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+       memory-region = <&c71_0_dma_memory_region>,
+                       <&c71_0_memory_region>;
+};
+
+&c71_1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
+       memory-region = <&c71_1_dma_memory_region>,
+                       <&c71_1_memory_region>;
+};
+
+&c71_2 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
+       memory-region = <&c71_2_dma_memory_region>,
+                       <&c71_2_memory_region>;
+};
+
+&c71_3 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
+       memory-region = <&c71_3_dma_memory_region>,
+                       <&c71_3_memory_region>;
+};