--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_GFX_STATE_COMMANDS_H_
+#define _XE_GFX_STATE_COMMANDS_H_
+
+#include "instructions/xe_instr_defs.h"
+
+#define GFX_STATE_OPCODE                       REG_GENMASK(28, 26)
+
+#define GFX_STATE_CMD(opcode) \
+       (XE_INSTR_GFX_STATE | REG_FIELD_PREP(GFX_STATE_OPCODE, opcode))
+
+#define STATE_WRITE_INLINE                     GFX_STATE_CMD(0x0)
+
+#endif
 
 #define GPGPU_CSR_BASE_ADDRESS                 GFXPIPE_COMMON_CMD(0x1, 0x4)
 #define STATE_COMPUTE_MODE                     GFXPIPE_COMMON_CMD(0x1, 0x5)
 #define CMD_3DSTATE_BTD                                GFXPIPE_COMMON_CMD(0x1, 0x6)
+#define STATE_SYSTEM_MEM_FENCE_ADDRESS         GFXPIPE_COMMON_CMD(0x1, 0x9)
+#define STATE_CONTEXT_DATA_BASE_ADDRESS                GFXPIPE_COMMON_CMD(0x1, 0xB)
 
 #define CMD_3DSTATE_VF_STATISTICS              GFXPIPE_SINGLE_DW_CMD(0x0, 0xB)
 
 #define CMD_3DSTATE_WM                         GFXPIPE_3D_CMD(0x0, 0x14)
 #define CMD_3DSTATE_CONSTANT_VS                        GFXPIPE_3D_CMD(0x0, 0x15)
 #define CMD_3DSTATE_CONSTANT_GS                        GFXPIPE_3D_CMD(0x0, 0x16)
+#define CMD_3DSTATE_CONSTANT_PS                        GFXPIPE_3D_CMD(0x0, 0x17)
 #define CMD_3DSTATE_SAMPLE_MASK                        GFXPIPE_3D_CMD(0x0, 0x18)
 #define CMD_3DSTATE_CONSTANT_HS                        GFXPIPE_3D_CMD(0x0, 0x19)
 #define CMD_3DSTATE_CONSTANT_DS                        GFXPIPE_3D_CMD(0x0, 0x1A)
 
 
 #include "instructions/xe_mi_commands.h"
 #include "instructions/xe_gfxpipe_commands.h"
+#include "instructions/xe_gfx_state_commands.h"
 #include "regs/xe_engine_regs.h"
 #include "regs/xe_gpu_commands.h"
 #include "regs/xe_lrc_layout.h"
        MATCH(GPGPU_CSR_BASE_ADDRESS);
        MATCH(STATE_COMPUTE_MODE);
        MATCH3D(3DSTATE_BTD);
+       MATCH(STATE_SYSTEM_MEM_FENCE_ADDRESS);
+       MATCH(STATE_CONTEXT_DATA_BASE_ADDRESS);
 
        MATCH3D(3DSTATE_VF_STATISTICS);
 
        MATCH3D(3DSTATE_WM);
        MATCH3D(3DSTATE_CONSTANT_VS);
        MATCH3D(3DSTATE_CONSTANT_GS);
+       MATCH3D(3DSTATE_CONSTANT_PS);
        MATCH3D(3DSTATE_SAMPLE_MASK);
        MATCH3D(3DSTATE_CONSTANT_HS);
        MATCH3D(3DSTATE_CONSTANT_DS);
        }
 }
 
+static int dump_gfx_state_command(struct drm_printer *p,
+                                 struct xe_gt *gt,
+                                 u32 *dw,
+                                 int remaining_dw)
+{
+       u32 numdw = instr_dw(*dw);
+       u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw);
+
+       /*
+        * Make sure we haven't mis-parsed a number of dwords that exceeds the
+        * remaining size of the LRC.
+        */
+       if (xe_gt_WARN_ON(gt, numdw > remaining_dw))
+               numdw = remaining_dw;
+
+       switch (*dw & (XE_INSTR_GFX_STATE | GFX_STATE_OPCODE)) {
+       MATCH(STATE_WRITE_INLINE);
+
+       default:
+               drm_printf(p, "[%#010x] unknown GFX_STATE command (opcode=%#x), likely %d dwords\n",
+                          *dw, opcode, numdw);
+               return numdw;
+       }
+}
+
 void xe_lrc_dump_default(struct drm_printer *p,
                         struct xe_gt *gt,
                         enum xe_engine_class hwe_class)
                        num_dw = dump_mi_command(p, gt, dw, remaining_dw);
                } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {
                        num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);
+               } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFX_STATE) {
+                       num_dw = dump_gfx_state_command(p, gt, dw, remaining_dw);
                } else {
                        num_dw = min(instr_dw(*dw), remaining_dw);
                        drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",