u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                        rt2x00_get_field32(word, TXD_W0_VALID));
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 2, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 2);
                rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
                rt2x00_desc_write(entry_priv->desc, 2, word);
 
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
                rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
                rt2x00_desc_write(entry_priv->desc, 1, word);
 
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, TXD_W0_VALID, 0);
                rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        /*
         * Start writing the descriptor words.
         */
-       rt2x00_desc_read(txd, 1, &word);
+       word = rt2x00_desc_read(txd, 1);
        rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
        rt2x00_desc_write(txd, 1, word);
 
-       rt2x00_desc_read(txd, 2, &word);
+       word = rt2x00_desc_read(txd, 2);
        rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
        rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
        rt2x00_desc_write(txd, 2, word);
 
-       rt2x00_desc_read(txd, 3, &word);
+       word = rt2x00_desc_read(txd, 3);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
        rt2x00_desc_write(txd, 3, word);
 
-       rt2x00_desc_read(txd, 4, &word);
+       word = rt2x00_desc_read(txd, 4);
        rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
                           txdesc->u.plcp.length_low);
        rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
         * the device, whereby the device may take hold of the TXD before we
         * finished updating it.
         */
-       rt2x00_desc_read(txd, 0, &word);
+       word = rt2x00_desc_read(txd, 0);
        rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
        rt2x00_set_field32(&word, TXD_W0_VALID, 1);
        rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
        u32 rx_low;
        u32 rx_high;
 
-       rt2x00_desc_read(entry_priv->desc, 0, &word0);
-       rt2x00_desc_read(entry_priv->desc, 2, &word2);
-       rt2x00_desc_read(entry_priv->desc, 3, &word3);
-       rt2x00_desc_read(entry_priv->desc, 4, &word4);
+       word0 = rt2x00_desc_read(entry_priv->desc, 0);
+       word2 = rt2x00_desc_read(entry_priv->desc, 2);
+       word3 = rt2x00_desc_read(entry_priv->desc, 3);
+       word4 = rt2x00_desc_read(entry_priv->desc, 4);
 
        if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
        while (!rt2x00queue_empty(queue)) {
                entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
                entry_priv = entry->priv_data;
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                    !rt2x00_get_field32(word, TXD_W0_VALID))
 
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                        rt2x00_get_field32(word, TXD_W0_VALID));
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
                rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
                rt2x00_desc_write(entry_priv->desc, 1, word);
 
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, TXD_W0_VALID, 0);
                rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        /*
         * Start writing the descriptor words.
         */
-       rt2x00_desc_read(txd, 1, &word);
+       word = rt2x00_desc_read(txd, 1);
        rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
        rt2x00_desc_write(txd, 1, word);
 
-       rt2x00_desc_read(txd, 2, &word);
+       word = rt2x00_desc_read(txd, 2);
        rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
        rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
        rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
        rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
        rt2x00_desc_write(txd, 2, word);
 
-       rt2x00_desc_read(txd, 3, &word);
+       word = rt2x00_desc_read(txd, 3);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
        rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
        rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
                           txdesc->u.plcp.length_high);
        rt2x00_desc_write(txd, 3, word);
 
-       rt2x00_desc_read(txd, 10, &word);
+       word = rt2x00_desc_read(txd, 10);
        rt2x00_set_field32(&word, TXD_W10_RTS,
                           test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
        rt2x00_desc_write(txd, 10, word);
         * the device, whereby the device may take hold of the TXD before we
         * finished updating it.
         */
-       rt2x00_desc_read(txd, 0, &word);
+       word = rt2x00_desc_read(txd, 0);
        rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
        rt2x00_set_field32(&word, TXD_W0_VALID, 1);
        rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
        u32 word0;
        u32 word2;
 
-       rt2x00_desc_read(entry_priv->desc, 0, &word0);
-       rt2x00_desc_read(entry_priv->desc, 2, &word2);
+       word0 = rt2x00_desc_read(entry_priv->desc, 0);
+       word2 = rt2x00_desc_read(entry_priv->desc, 2);
 
        if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
        while (!rt2x00queue_empty(queue)) {
                entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
                entry_priv = entry->priv_data;
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                    !rt2x00_get_field32(word, TXD_W0_VALID))
 
        /*
         * Start writing the descriptor words.
         */
-       rt2x00_desc_read(txd, 0, &word);
+       word = rt2x00_desc_read(txd, 0);
        rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
        rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
                           test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
        rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
        rt2x00_desc_write(txd, 0, word);
 
-       rt2x00_desc_read(txd, 1, &word);
+       word = rt2x00_desc_read(txd, 1);
        rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
        rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
        rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
        rt2x00_desc_write(txd, 1, word);
 
-       rt2x00_desc_read(txd, 2, &word);
+       word = rt2x00_desc_read(txd, 2);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
        rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
        /*
         * It is now safe to read the descriptor on all architectures.
         */
-       rt2x00_desc_read(rxd, 0, &word0);
-       rt2x00_desc_read(rxd, 1, &word1);
+       word0 = rt2x00_desc_read(rxd, 0);
+       word1 = rt2x00_desc_read(rxd, 1);
 
        if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
                rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
 
        if (rxdesc->cipher != CIPHER_NONE) {
-               _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
-               _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
+               rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2);
+               rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3);
                rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
 
                /* ICV is located at the end of frame */
 
        /*
         * Initialize TX Info descriptor
         */
-       rt2x00_desc_read(txwi, 0, &word);
+       word = rt2x00_desc_read(txwi, 0);
        rt2x00_set_field32(&word, TXWI_W0_FRAG,
                           test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
        rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
        rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
        rt2x00_desc_write(txwi, 0, word);
 
-       rt2x00_desc_read(txwi, 1, &word);
+       word = rt2x00_desc_read(txwi, 1);
        rt2x00_set_field32(&word, TXWI_W1_ACK,
                           test_bit(ENTRY_TXD_ACK, &txdesc->flags));
        rt2x00_set_field32(&word, TXWI_W1_NSEQ,
        __le32 *rxwi = (__le32 *) entry->skb->data;
        u32 word;
 
-       rt2x00_desc_read(rxwi, 0, &word);
+       word = rt2x00_desc_read(rxwi, 0);
 
        rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
        rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 
-       rt2x00_desc_read(rxwi, 1, &word);
+       word = rt2x00_desc_read(rxwi, 1);
 
        if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
                rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
        if (rxdesc->rate_mode == RATE_MODE_CCK)
                rxdesc->signal &= ~0x8;
 
-       rt2x00_desc_read(rxwi, 2, &word);
+       word = rt2x00_desc_read(rxwi, 2);
 
        /*
         * Convert descriptor AGC value to RSSI value.
         * Obtain the status about this packet.
         */
        txdesc.flags = 0;
-       rt2x00_desc_read(txwi, 0, &word);
+       word = rt2x00_desc_read(txwi, 0);
 
        mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
        ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 
        __le32 *rxd = entry_priv->desc;
        u32 word;
 
-       rt2x00_desc_read(rxd, 3, &word);
+       word = rt2x00_desc_read(rxd, 3);
 
        if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
        wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
 
        txwi = rt2800_drv_get_txwi(entry);
-       rt2x00_desc_read(txwi, 1, &word);
+       word = rt2x00_desc_read(txwi, 1);
        tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 
        return (tx_wcid == wcid);
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
 
                return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
        } else {
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
 
                return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
        }
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
                rt2x00_desc_write(entry_priv->desc, 0, word);
 
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
                rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
                rt2x00_desc_write(entry_priv->desc, 1, word);
 
                rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
                                          entry->entry_idx);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 1, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 1);
                rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
                rt2x00_desc_write(entry_priv->desc, 1, word);
        }
 
        /*
         * Initialize TXINFO descriptor
         */
-       rt2x00_desc_read(txi, 0, &word);
+       word = rt2x00_desc_read(txi, 0);
 
        /*
         * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is
         */
        txwi = rt2800usb_get_txwi(entry);
 
-       rt2x00_desc_read(txwi, 1, &word);
+       word = rt2x00_desc_read(txwi, 1);
        tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
        tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
        tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
         * | RXINFO | RXWI | header | L2 pad | payload | pad | RXD | USB pad |
         *          |<------------ rx_pkt_len -------------->|
         */
-       rt2x00_desc_read(rxi, 0, &word);
+       word = rt2x00_desc_read(rxi, 0);
        rx_pkt_len = rt2x00_get_field32(word, RXINFO_W0_USB_DMA_RX_PKT_LEN);
 
        /*
        /*
         * It is now safe to read the descriptor on all architectures.
         */
-       rt2x00_desc_read(rxd, 0, &word);
+       word = rt2x00_desc_read(rxd, 0);
 
        if (rt2x00_get_field32(word, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 
  * _rt2x00_desc_read - Read a word from the hardware descriptor.
  * @desc: Base descriptor address
  * @word: Word index from where the descriptor should be read.
- * @value: Address where the descriptor value should be written into.
  */
-static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value)
+static inline __le32 _rt2x00_desc_read(__le32 *desc, const u8 word)
 {
-       *value = desc[word];
+       return desc[word];
 }
 
 /**
  * function will take care of the byte ordering.
  * @desc: Base descriptor address
  * @word: Word index from where the descriptor should be read.
- * @value: Address where the descriptor value should be written into.
  */
-static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value)
+static inline u32 rt2x00_desc_read(__le32 *desc, const u8 word)
 {
-       __le32 tmp;
-       _rt2x00_desc_read(desc, word, &tmp);
-       *value = le32_to_cpu(tmp);
+       return le32_to_cpu(_rt2x00_desc_read(desc, word));
 }
 
 /**
 
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                        rt2x00_get_field32(word, TXD_W0_VALID));
        u32 word;
 
        if (entry->queue->qid == QID_RX) {
-               rt2x00_desc_read(entry_priv->desc, 5, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 5);
                rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
                                   skbdesc->skb_dma);
                rt2x00_desc_write(entry_priv->desc, 5, word);
 
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        } else {
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
                rt2x00_set_field32(&word, TXD_W0_VALID, 0);
                rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
                rt2x00_desc_write(entry_priv->desc, 0, word);
        /*
         * Start writing the descriptor words.
         */
-       rt2x00_desc_read(txd, 1, &word);
+       word = rt2x00_desc_read(txd, 1);
        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
        rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
        rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
        rt2x00_desc_write(txd, 1, word);
 
-       rt2x00_desc_read(txd, 2, &word);
+       word = rt2x00_desc_read(txd, 2);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
        rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
                _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
        }
 
-       rt2x00_desc_read(txd, 5, &word);
+       word = rt2x00_desc_read(txd, 5);
        rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
        rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
        rt2x00_set_field32(&word, TXD_W5_TX_POWER,
        rt2x00_desc_write(txd, 5, word);
 
        if (entry->queue->qid != QID_BEACON) {
-               rt2x00_desc_read(txd, 6, &word);
+               word = rt2x00_desc_read(txd, 6);
                rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
                                   skbdesc->skb_dma);
                rt2x00_desc_write(txd, 6, word);
 
-               rt2x00_desc_read(txd, 11, &word);
+               word = rt2x00_desc_read(txd, 11);
                rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
                                   txdesc->length);
                rt2x00_desc_write(txd, 11, word);
         * the device, whereby the device may take hold of the TXD before we
         * finished updating it.
         */
-       rt2x00_desc_read(txd, 0, &word);
+       word = rt2x00_desc_read(txd, 0);
        rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
        rt2x00_set_field32(&word, TXD_W0_VALID, 1);
        rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
        u32 word0;
        u32 word1;
 
-       rt2x00_desc_read(entry_priv->desc, 0, &word0);
-       rt2x00_desc_read(entry_priv->desc, 1, &word1);
+       word0 = rt2x00_desc_read(entry_priv->desc, 0);
+       word1 = rt2x00_desc_read(entry_priv->desc, 1);
 
        if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
        rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
 
        if (rxdesc->cipher != CIPHER_NONE) {
-               _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
-               _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
+               rxdesc->iv[0] = _rt2x00_desc_read(entry_priv->desc, 2);
+               rxdesc->iv[1] = _rt2x00_desc_read(entry_priv->desc, 3);
                rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
 
-               _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
+               rxdesc->icv = _rt2x00_desc_read(entry_priv->desc, 4);
                rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
 
                /*
 
                entry = &queue->entries[index];
                entry_priv = entry->priv_data;
-               rt2x00_desc_read(entry_priv->desc, 0, &word);
+               word = rt2x00_desc_read(entry_priv->desc, 0);
 
                if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
                    !rt2x00_get_field32(word, TXD_W0_VALID))
 
        /*
         * Start writing the descriptor words.
         */
-       rt2x00_desc_read(txd, 0, &word);
+       word = rt2x00_desc_read(txd, 0);
        rt2x00_set_field32(&word, TXD_W0_BURST,
                           test_bit(ENTRY_TXD_BURST, &txdesc->flags));
        rt2x00_set_field32(&word, TXD_W0_VALID, 1);
        rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
        rt2x00_desc_write(txd, 0, word);
 
-       rt2x00_desc_read(txd, 1, &word);
+       word = rt2x00_desc_read(txd, 1);
        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
        rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
                           test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
        rt2x00_desc_write(txd, 1, word);
 
-       rt2x00_desc_read(txd, 2, &word);
+       word = rt2x00_desc_read(txd, 2);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
        rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
        rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
                _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
        }
 
-       rt2x00_desc_read(txd, 5, &word);
+       word = rt2x00_desc_read(txd, 5);
        rt2x00_set_field32(&word, TXD_W5_TX_POWER,
                           TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
        rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
        /*
         * It is now safe to read the descriptor on all architectures.
         */
-       rt2x00_desc_read(rxd, 0, &word0);
-       rt2x00_desc_read(rxd, 1, &word1);
+       word0 = rt2x00_desc_read(rxd, 0);
+       word1 = rt2x00_desc_read(rxd, 1);
 
        if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
        rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
 
        if (rxdesc->cipher != CIPHER_NONE) {
-               _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
-               _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
+               rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2);
+               rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3);
                rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
 
-               _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
+               rxdesc->icv = _rt2x00_desc_read(rxd, 4);
                rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
 
                /*