struct clk_onecell_data onecell;
        struct rsnd_mod mod;
        u32 flags;
+       u32 ckr;
+       u32 rbga;
+       u32 rbgb;
 
        int rbga_rate_for_441khz; /* RBGA */
        int rbgb_rate_for_48khz;  /* RBGB */
        struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
        struct device *dev = rsnd_priv_to_dev(priv);
+       struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
        struct clk *clk;
        int i;
        u32 data;
+       u32 ckr = 0;
        int sel_table[] = {
                [CLKA] = 0x1,
                [CLKB] = 0x2,
        rsnd_adg_set_ssi_clk(ssi_mod, data);
 
        if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
-               struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
-               u32 ckr = 0;
-
                if (0 == (rate % 8000))
                        ckr = 0x80000000;
-
-               rsnd_mod_bset(adg_mod, BRGCKR, 0x80000000, ckr);
        }
 
+       rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
+       rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
+       rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
+
        dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
                rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
                data, rate);
                                struct rsnd_adg *adg)
 {
        struct clk *clk;
-       struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
        struct device *dev = rsnd_priv_to_dev(priv);
        struct device_node *np = dev->of_node;
        u32 ckr, rbgx, rbga, rbgb;
                }
        }
 
-       rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, ckr);
-       rsnd_mod_write(adg_mod, BRRA,  rbga);
-       rsnd_mod_write(adg_mod, BRRB,  rbgb);
+       adg->ckr = ckr;
+       adg->rbga = rbga;
+       adg->rbgb = rbgb;
 
        for_each_rsnd_clkout(clk, adg, i)
                dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));