Earlier chips only had two performance levels, but newer
ones potentially had more.  The message is harmless.  Drop the
message to avoid spamming the log.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1874
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
                        request_ps->classification.ui_label);
        data->mclk_ignore_signal = false;
 
-       PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
-                                "VI should always have 2 performance levels",
-                               );
-
        max_limits = adev->pm.ac_power ?
                        &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
                        &(hwmgr->dyn_state.max_clock_voltage_on_dc);