u16 flex_byte);
 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
                                       u8 l4type);
+extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
+                                   struct ixgbe_ring *ring);
+extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
+                               struct ixgbe_ring *ring);
 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 #ifdef IXGBE_FCOE
 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 
                         struct ixgbe_dcb_config *dcb_config)
 {
        s32 ret = 0;
-       if (hw->mac.type == ixgbe_mac_82598EB)
+       switch (hw->mac.type) {
+       case ixgbe_mac_82598EB:
                ret = ixgbe_dcb_hw_config_82598(hw, dcb_config);
-       else if (hw->mac.type == ixgbe_mac_82599EB)
+               break;
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                ret = ixgbe_dcb_hw_config_82599(hw, dcb_config);
+               break;
+       default:
+               break;
+       }
        return ret;
 }
 
 
                        netdev->netdev_ops->ndo_stop(netdev);
                ixgbe_clear_interrupt_scheme(adapter);
 
-               if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+               adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
+               switch (adapter->hw.mac.type) {
+               case ixgbe_mac_82598EB:
                        adapter->last_lfc_mode = adapter->hw.fc.current_mode;
                        adapter->hw.fc.requested_mode = ixgbe_fc_none;
-               }
-               adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
-               if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+                       break;
+               case ixgbe_mac_82599EB:
+               case ixgbe_mac_X540:
                        adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
                        adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
+                       break;
+               default:
+                       break;
                }
+
                adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
                ixgbe_init_interrupt_scheme(adapter);
                if (netif_running(netdev))
                        adapter->dcb_cfg.pfc_mode_enable = false;
                        adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
                        adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
-                       if (adapter->hw.mac.type == ixgbe_mac_82599EB)
+                       switch (adapter->hw.mac.type) {
+                       case ixgbe_mac_82599EB:
+                       case ixgbe_mac_X540:
                                adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
+                               break;
+                       default:
+                               break;
+                       }
 
                        ixgbe_init_interrupt_scheme(adapter);
                        if (netif_running(netdev))
        for (i = 0; i < netdev->addr_len; i++)
                perm_addr[i] = adapter->hw.mac.perm_addr[i];
 
-       if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+       switch (adapter->hw.mac.type) {
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                for (j = 0; j < netdev->addr_len; j++, i++)
                        perm_addr[i] = adapter->hw.mac.san_addr[j];
+               break;
+       default:
+               break;
        }
 }
 
        }
 
        if (adapter->dcb_cfg.pfc_mode_enable) {
-               if ((adapter->hw.mac.type != ixgbe_mac_82598EB) &&
-                       (adapter->hw.fc.current_mode != ixgbe_fc_pfc))
-                       adapter->last_lfc_mode = adapter->hw.fc.current_mode;
+               switch (adapter->hw.mac.type) {
+               case ixgbe_mac_82599EB:
+               case ixgbe_mac_X540:
+                       if (adapter->hw.fc.current_mode != ixgbe_fc_pfc)
+                               adapter->last_lfc_mode =
+                                                 adapter->hw.fc.current_mode;
+                       break;
+               default:
+                       break;
+               }
                adapter->hw.fc.requested_mode = ixgbe_fc_pfc;
        } else {
-               if (adapter->hw.mac.type != ixgbe_mac_82598EB)
-                       adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
-               else
+               switch (adapter->hw.mac.type) {
+               case ixgbe_mac_82598EB:
                        adapter->hw.fc.requested_mode = ixgbe_fc_none;
+                       break;
+               case ixgbe_mac_82599EB:
+               case ixgbe_mac_X540:
+                       adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
+                       break;
+               default:
+                       break;
+               }
        }
 
        if (adapter->dcb_set_bitmap & BIT_RESETLINK) {
 
 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 {
        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       u32 feature_list;
 
-       if (data) {
-               netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
-               if (adapter->hw.mac.type == ixgbe_mac_82599EB)
-                       netdev->features |= NETIF_F_SCTP_CSUM;
-       } else {
-               netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
-                                     NETIF_F_SCTP_CSUM);
+       feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+       switch (adapter->hw.mac.type) {
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
+               feature_list |= NETIF_F_SCTP_CSUM;
+               break;
+       default:
+               break;
        }
+       if (data)
+               netdev->features |= feature_list;
+       else
+               netdev->features &= ~feature_list;
 
        return 0;
 }
                test = reg_test_82598;
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                toggle = 0x7FFFF30F;
                test = reg_test_82599;
                break;
 
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
                reg_ctl &= ~IXGBE_DMATXCTL_TE;
                IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
 
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
                reg_data |= IXGBE_DMATXCTL_TE;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
                        case ixgbe_mac_82599EB:
                                need_reset = true;
                                break;
+                       case ixgbe_mac_X540: {
+                               int i;
+                               for (i = 0; i < adapter->num_rx_queues; i++) {
+                                       struct ixgbe_ring *ring =
+                                                         adapter->rx_ring[i];
+                                       if (adapter->flags2 &
+                                           IXGBE_FLAG2_RSC_ENABLED) {
+                                               ixgbe_configure_rscctl(adapter,
+                                                                      ring);
+                                       } else {
+                                               ixgbe_clear_rscctl(adapter,
+                                                                  ring);
+                                       }
+                               }
+                       }
+                               break;
                        default:
                                break;
                        }
 
         board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
         board_82599 },
+       {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
+        board_82599 },
 
        /* required last entry */
        {0, }
                IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                if (direction == -1) {
                        /* other causes */
                        msix_vector |= IXGBE_IVAR_ALLOC_VAL;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
                mask = (qmask >> 32);
                rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
                rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
                           IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
                txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
                txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
                               v_idx);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                ixgbe_set_ivar(adapter, -1, 1, v_idx);
                break;
 
                itr_reg |= (itr_reg << 16);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                /*
-                * 82599 can support a value of zero, so allow it for
+                * 82599 and X540 can support a value of zero, so allow it for
                 * max interrupt rate, but there is an errata where it can
                 * not be zero with RSC
                 */
 
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                /* Handle Flow Director Full threshold interrupt */
                if (eicr & IXGBE_EICR_FLOW_DIR) {
                        int i;
                IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
                IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
                mask |= IXGBE_EIMS_GPI_SDP1;
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                mask |= IXGBE_EIMS_ECC;
                mask |= IXGBE_EIMS_GPI_SDP1;
                mask |= IXGBE_EIMS_GPI_SDP2;
 
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                ixgbe_check_sfp_event(adapter, eicr);
                if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
                    ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
        }
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
        default:
                break;
        }
        IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
 }
 
+/**
+ * ixgbe_clear_rscctl - disable RSC for the indicated ring
+ * @adapter: address of board private structure
+ * @ring: structure containing ring specific data
+ **/
+void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
+                        struct ixgbe_ring *ring)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 rscctrl;
+       u8 reg_idx = ring->reg_idx;
+
+       rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
+       rscctrl &= ~IXGBE_RSCCTL_RSCEN;
+       IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
+}
+
 /**
  * ixgbe_configure_rscctl - enable RSC for the indicated ring
  * @adapter:    address of board private structure
  * @index:      index of ring to set
  **/
-static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
+void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
                                   struct ixgbe_ring *ring)
 {
        struct ixgbe_hw *hw = &adapter->hw;
                rdrxctl |= IXGBE_RDRXCTL_MVMEN;
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                /* Disable RSC for ACK packets */
                IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
                   (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
                IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                for (i = 0; i < adapter->num_rx_queues; i++) {
                        j = adapter->rx_ring[i]->reg_idx;
                        vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
                IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                for (i = 0; i < adapter->num_rx_queues; i++) {
                        j = adapter->rx_ring[i]->reg_idx;
                        vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
                case ixgbe_mac_82598EB:
                        IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
                        break;
-               default:
                case ixgbe_mac_82599EB:
+               case ixgbe_mac_X540:
+               default:
                        IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
                        IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
                        break;
        /* Disable the Tx DMA engine on 82599 */
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
                                (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
                                 ~IXGBE_DMATXCTL_TE));
                ret = true;
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                if (dcb_i == 8) {
                        /*
                         * Tx TC0 starts at: descriptor queue 0
                adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
                adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
                adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
                pci_wake_from_d3(pdev, false);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                pci_wake_from_d3(pdev, !!wufc);
                break;
        default:
                                IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
                        break;
                case ixgbe_mac_82599EB:
+               case ixgbe_mac_X540:
                        hwstats->pxonrxc[i] +=
                                IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
                        break;
                hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
                break;
        case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
                IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
                hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
                                flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
                        }
                                break;
-                       case ixgbe_mac_82599EB: {
+                       case ixgbe_mac_82599EB:
+                       case ixgbe_mac_X540: {
                                u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
                                u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
                                flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
                goto err_sw_init;
 
        /* Make it possible the adapter to be woken up via WOL */
-       if (adapter->hw.mac.type == ixgbe_mac_82599EB)
+       switch (adapter->hw.mac.type) {
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
+               break;
+       default:
+               break;
+       }
 
        /*
         * If there is a fan on this device and it has failed log the
 
        u32 vflre = 0;
        s32 ret_val = IXGBE_ERR_MBX;
 
-       if (hw->mac.type == ixgbe_mac_82599EB)
+       switch (hw->mac.type) {
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
                vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
+               break;
+       default:
+               break;
+       }
 
        if (vflre & (1 << vf_shift)) {
                ret_val = 0;
 {
        struct ixgbe_mbx_info *mbx = &hw->mbx;
 
-       if (hw->mac.type != ixgbe_mac_82599EB)
-               return;
-
-       mbx->timeout = 0;
-       mbx->usec_delay = 0;
-
-       mbx->size = IXGBE_VFMAILBOX_SIZE;
-
-       mbx->stats.msgs_tx = 0;
-       mbx->stats.msgs_rx = 0;
-       mbx->stats.reqs = 0;
-       mbx->stats.acks = 0;
-       mbx->stats.rsts = 0;
+       switch (hw->mac.type) {
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
+               mbx->timeout = 0;
+               mbx->usec_delay = 0;
+
+               mbx->size = IXGBE_VFMAILBOX_SIZE;
+
+               mbx->stats.msgs_tx = 0;
+               mbx->stats.msgs_rx = 0;
+               mbx->stats.reqs = 0;
+               mbx->stats.acks = 0;
+               mbx->stats.rsts = 0;
+               break;
+       default:
+               break;
+       }
 }
 
 struct ixgbe_mbx_operations mbx_ops_generic = {
 
 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
+#define IXGBE_DEV_ID_X540T               0x1528
 
 /* General Registers */
 #define IXGBE_CTRL      0x00000
 
 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
 
-enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
+static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 {
        return ixgbe_media_type_copper;
 }
  *  @autoneg: true if autonegotiation enabled
  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  **/
-s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
-                              ixgbe_link_speed speed, bool autoneg,
-                              bool autoneg_wait_to_complete)
+static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
+                                     ixgbe_link_speed speed, bool autoneg,
+                                     bool autoneg_wait_to_complete)
 {
        return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
                                            autoneg_wait_to_complete);
  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  *  reset.
  **/
-s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
+static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 {
        ixgbe_link_speed link_speed;
        s32 status = 0;
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
+static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 {
        u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u16 ext_ability = 0;
  * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
  * @hw: pointer to hardware structure
  **/
-s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
+static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 {
        struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
        u32 eec;
  * @offset: offset of word in the EEPROM to read
  * @data: word read from the EERPOM
  **/
-s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
+static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 {
        s32 status;
 
  *
  * Write a 16 bit word to the EEPROM using the EEWR register.
  **/
-s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
+static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
        u32 eewr;
        s32 status;
  * checksum and updates the EEPROM and instructs the hardware to update
  * the flash.
  **/
-s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
+static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 {
        s32 status;