+++ /dev/null
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#include "atom.h"
-#include "amdgpu.h"
-#include "amd_shared.h"
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include "amdgpu_pm.h"
-#include <drm/amdgpu_drm.h>
-#include "amdgpu_powerplay.h"
-#include "si_dpm.h"
-#include "cik_dpm.h"
-#include "vi_dpm.h"
-
-static int amdgpu_pp_early_init(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- struct amd_powerplay *amd_pp;
- int ret = 0;
-
- amd_pp = &(adev->powerplay);
- amd_pp->pp_handle = (void *)adev;
-
- switch (adev->asic_type) {
- case CHIP_POLARIS11:
- case CHIP_POLARIS10:
- case CHIP_POLARIS12:
- case CHIP_TONGA:
- case CHIP_FIJI:
- case CHIP_TOPAZ:
- case CHIP_CARRIZO:
- case CHIP_STONEY:
- case CHIP_VEGA10:
- case CHIP_RAVEN:
- amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
- amd_pp->ip_funcs = &pp_ip_funcs;
- amd_pp->pp_funcs = &pp_dpm_funcs;
- break;
- /* These chips don't have powerplay implemenations */
-#ifdef CONFIG_DRM_AMDGPU_SI
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- case CHIP_VERDE:
- case CHIP_OLAND:
- case CHIP_HAINAN:
- amd_pp->ip_funcs = &si_dpm_ip_funcs;
- amd_pp->pp_funcs = &si_dpm_funcs;
- break;
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
- case CHIP_BONAIRE:
- case CHIP_HAWAII:
- if (amdgpu_dpm == -1) {
- amd_pp->ip_funcs = &ci_dpm_ip_funcs;
- amd_pp->pp_funcs = &ci_dpm_funcs;
- } else {
- amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
- amd_pp->ip_funcs = &pp_ip_funcs;
- amd_pp->pp_funcs = &pp_dpm_funcs;
- }
- break;
- case CHIP_KABINI:
- case CHIP_MULLINS:
- case CHIP_KAVERI:
- amd_pp->ip_funcs = &kv_dpm_ip_funcs;
- amd_pp->pp_funcs = &kv_dpm_funcs;
- break;
-#endif
- default:
- ret = -EINVAL;
- break;
- }
-
- if (adev->powerplay.ip_funcs->early_init)
- ret = adev->powerplay.ip_funcs->early_init(adev);
-
- return ret;
-}
-
-
-static int amdgpu_pp_late_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->late_init)
- ret = adev->powerplay.ip_funcs->late_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_sw_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->sw_init)
- ret = adev->powerplay.ip_funcs->sw_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_sw_fini(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->sw_fini)
- ret = adev->powerplay.ip_funcs->sw_fini(
- adev->powerplay.pp_handle);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static int amdgpu_pp_hw_init(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_init_bo(adev);
-
- if (adev->powerplay.ip_funcs->hw_init)
- ret = adev->powerplay.ip_funcs->hw_init(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static int amdgpu_pp_hw_fini(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->hw_fini)
- ret = adev->powerplay.ip_funcs->hw_fini(
- adev->powerplay.pp_handle);
-
- return ret;
-}
-
-static void amdgpu_pp_late_fini(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->late_fini)
- adev->powerplay.ip_funcs->late_fini(
- adev->powerplay.pp_handle);
-
- if (adev->powerplay.cgs_device)
- amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
-}
-
-static int amdgpu_pp_suspend(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->suspend)
- ret = adev->powerplay.ip_funcs->suspend(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_resume(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->resume)
- ret = adev->powerplay.ip_funcs->resume(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_set_clockgating_state(void *handle,
- enum amd_clockgating_state state)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->set_clockgating_state)
- ret = adev->powerplay.ip_funcs->set_clockgating_state(
- adev->powerplay.pp_handle, state);
- return ret;
-}
-
-static int amdgpu_pp_set_powergating_state(void *handle,
- enum amd_powergating_state state)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->set_powergating_state)
- ret = adev->powerplay.ip_funcs->set_powergating_state(
- adev->powerplay.pp_handle, state);
- return ret;
-}
-
-
-static bool amdgpu_pp_is_idle(void *handle)
-{
- bool ret = true;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->is_idle)
- ret = adev->powerplay.ip_funcs->is_idle(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_wait_for_idle(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->wait_for_idle)
- ret = adev->powerplay.ip_funcs->wait_for_idle(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static int amdgpu_pp_soft_reset(void *handle)
-{
- int ret = 0;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->soft_reset)
- ret = adev->powerplay.ip_funcs->soft_reset(
- adev->powerplay.pp_handle);
- return ret;
-}
-
-static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- .name = "amdgpu_powerplay",
- .early_init = amdgpu_pp_early_init,
- .late_init = amdgpu_pp_late_init,
- .sw_init = amdgpu_pp_sw_init,
- .sw_fini = amdgpu_pp_sw_fini,
- .hw_init = amdgpu_pp_hw_init,
- .hw_fini = amdgpu_pp_hw_fini,
- .late_fini = amdgpu_pp_late_fini,
- .suspend = amdgpu_pp_suspend,
- .resume = amdgpu_pp_resume,
- .is_idle = amdgpu_pp_is_idle,
- .wait_for_idle = amdgpu_pp_wait_for_idle,
- .soft_reset = amdgpu_pp_soft_reset,
- .set_clockgating_state = amdgpu_pp_set_clockgating_state,
- .set_powergating_state = amdgpu_pp_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
-{
- .type = AMD_IP_BLOCK_TYPE_SMC,
- .major = 1,
- .minor = 0,
- .rev = 0,
- .funcs = &amdgpu_pp_ip_funcs,
-};
#include <linux/slab.h>
#include "amd_shared.h"
#include "amd_powerplay.h"
-#include "pp_instance.h"
#include "power_state.h"
#include "amdgpu.h"
#include "hwmgr.h"
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
-static inline int pp_check(struct pp_instance *handle)
-{
- if (handle == NULL)
- return -EINVAL;
+static const struct amd_pm_funcs pp_dpm_funcs;
- if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
+static inline int pp_check(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
return -EINVAL;
- if (handle->pm_en == 0)
- return PP_DPM_DISABLED;
-
- if (handle->hwmgr->hwmgr_func == NULL)
+ if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
return PP_DPM_DISABLED;
return 0;
static int amd_powerplay_create(struct amdgpu_device *adev)
{
- struct pp_instance *instance;
+ struct pp_hwmgr *hwmgr;
if (adev == NULL)
return -EINVAL;
- instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
- if (instance == NULL)
+ hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
+ if (hwmgr == NULL)
return -ENOMEM;
- instance->parent = adev;
- instance->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
- instance->device = adev->powerplay.cgs_device;
- mutex_init(&instance->pp_lock);
- adev->powerplay.pp_handle = instance;
-
+ hwmgr->adev = adev;
+ hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
+ hwmgr->device = amdgpu_cgs_create_device(adev);
+ mutex_init(&hwmgr->smu_lock);
+ hwmgr->chip_family = adev->family;
+ hwmgr->chip_id = adev->asic_type;
+ hwmgr->feature_mask = amdgpu_pp_feature_mask;
+ adev->powerplay.pp_handle = hwmgr;
+ adev->powerplay.pp_funcs = &pp_dpm_funcs;
return 0;
}
-static int amd_powerplay_destroy(void *handle)
+static int amd_powerplay_destroy(struct amdgpu_device *adev)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- kfree(instance->hwmgr->hardcode_pp_table);
- instance->hwmgr->hardcode_pp_table = NULL;
+ kfree(hwmgr->hardcode_pp_table);
+ hwmgr->hardcode_pp_table = NULL;
- kfree(instance->hwmgr);
- instance->hwmgr = NULL;
+ kfree(hwmgr);
+ hwmgr = NULL;
- kfree(instance);
- instance = NULL;
return 0;
}
static int pp_early_init(void *handle)
{
int ret;
- struct pp_instance *pp_handle = NULL;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = handle;
ret = amd_powerplay_create(adev);
if (ret != 0)
return ret;
- pp_handle = adev->powerplay.pp_handle;
-
- ret = hwmgr_early_init(pp_handle);
+ ret = hwmgr_early_init(adev->powerplay.pp_handle);
if (ret)
return -EINVAL;
static int pp_sw_init(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->smu_init == NULL)
return -EINVAL;
pr_debug("amdgpu: powerplay sw initialized\n");
}
+
return ret;
}
static int pp_sw_fini(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->smumgr_funcs->smu_fini == NULL)
- return -EINVAL;
-
- ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ if (hwmgr->smumgr_funcs->smu_fini != NULL)
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
}
- return ret;
+ return 0;
}
static int pp_hw_init(void *handle)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- ret = pp_check(pp_handle);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ amdgpu_ucode_init_bo(adev);
- if (ret >= 0) {
- hwmgr = pp_handle->hwmgr;
+ ret = pp_check(hwmgr);
+ if (ret >= 0) {
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
goto exit;
- ret = hwmgr_hw_init(pp_handle);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
goto exit;
}
return ret;
exit:
- pp_handle->pm_en = 0;
+ hwmgr->pm_en = 0;
cgs_notify_dpm_enabled(hwmgr->device, false);
return 0;
static int pp_hw_fini(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_fini(pp_handle);
+ hwmgr_hw_fini(hwmgr);
return 0;
}
static int pp_late_init(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
+
if (ret == 0)
- pp_dpm_dispatch_tasks(pp_handle,
+ pp_dpm_dispatch_tasks(hwmgr,
AMD_PP_TASK_COMPLETE_INIT, NULL);
return 0;
static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
static int pp_suspend(void *handle)
{
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret == 0)
- hwmgr_hw_suspend(pp_handle);
+ hwmgr_hw_suspend(hwmgr);
return 0;
}
static int pp_resume(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct amdgpu_device *adev = handle;
+ struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret < 0)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
return -EINVAL;
}
if (ret == PP_DPM_DISABLED)
return 0;
- return hwmgr_hw_resume(pp_handle);
+ return hwmgr_hw_resume(hwmgr);
}
-const struct amd_ip_funcs pp_ip_funcs = {
+static const struct amd_ip_funcs pp_ip_funcs = {
.name = "powerplay",
.early_init = pp_early_init,
.late_init = pp_late_init,
.set_powergating_state = pp_set_powergating_state,
};
+const struct amdgpu_ip_block_version pp_smu_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &pp_ip_funcs,
+};
+
static int pp_dpm_load_fw(void *handle)
{
return 0;
static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (level == hwmgr->dpm_level)
return 0;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
pp_dpm_en_umd_pstate(hwmgr, &level);
hwmgr->request_dpm_level = level;
- hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
- mutex_unlock(&pp_handle->pp_lock);
+ hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static enum amd_dpm_forced_level pp_dpm_get_performance_level(
void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
enum amd_dpm_forced_level level;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
level = hwmgr->dpm_level;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return level;
}
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t clk = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return clk;
}
static void pp_dpm_powergate_vce(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state)
{
int ret = 0;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr_handle_task(pp_handle, task_id, user_state);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr_handle_task(hwmgr, task_id, user_state);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
struct pp_power_state *state;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
enum amd_pm_state_type pm_type;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->current_ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
state = hwmgr->current_ps;
pm_type = POWER_STATE_TYPE_DEFAULT;
break;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return pm_type;
}
static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
}
static uint32_t pp_dpm_get_fan_control_mode(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
uint32_t mode = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return mode;
}
static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_pp_num_states(void *handle,
struct pp_states_info *data)
{
- struct pp_hwmgr *hwmgr;
+ struct pp_hwmgr *hwmgr = handle;
int i;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
memset(data, 0, sizeof(*data));
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->ps == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
data->nums = hwmgr->num_ps;
data->states[i] = POWER_STATE_TYPE_DEFAULT;
}
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_dpm_get_pp_table(void *handle, char **table)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
int size = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (!hwmgr->soft_pp_table)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
*table = (char *)hwmgr->soft_pp_table;
size = hwmgr->soft_pp_table_size;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return size;
}
static int amd_powerplay_reset(void *handle)
{
- struct pp_instance *instance = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret;
- ret = pp_check(instance);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- ret = pp_hw_fini(instance);
+ ret = pp_hw_fini(hwmgr);
if (ret)
return ret;
- ret = hwmgr_hw_init(instance);
+ ret = hwmgr_hw_init(hwmgr);
if (ret)
return ret;
- return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL);
+ return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
}
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (!hwmgr->hardcode_pp_table) {
hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
hwmgr->soft_pp_table_size,
GFP_KERNEL);
if (!hwmgr->hardcode_pp_table) {
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -ENOMEM;
}
}
memcpy(hwmgr->hardcode_pp_table, buf, size);
hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
ret = amd_powerplay_reset(handle);
if (ret)
static int pp_dpm_force_clock_level(void *handle,
enum pp_clock_type type, uint32_t mask)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->force_clock_level == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
else
ret = -EINVAL;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_print_clock_levels(void *handle,
enum pp_clock_type type, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_sclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_get_mclk_od(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (value == NULL)
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
switch (idx) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)value) = hwmgr->pstate_sclk;
*((uint32_t *)value) = hwmgr->pstate_mclk;
return 0;
default:
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
}
static struct amd_vce_state*
pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return NULL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr && idx < hwmgr->num_vce_state_tables)
return &hwmgr->vce_states[idx];
return NULL;
static int pp_get_power_profile_mode(void *handle, char *buf)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- if (!buf || pp_check(pp_handle))
+ if (!buf || pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return snprintf(buf, PAGE_SIZE, "\n");
static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = -EINVAL;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
static int pp_dpm_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type, bool en)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
long workload;
uint32_t index;
- if (pp_check(pp_handle))
+ if (pp_check(hwmgr))
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (!en) {
hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
uint32_t mc_addr_hi,
uint32_t size)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
}
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
virtual_addr_hi, mc_addr_low, mc_addr_hi,
size);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_power_limit(void *handle, uint32_t limit)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_power_limit == NULL) {
pr_info("%s was not implemented.\n", __func__);
return -EINVAL;
if (limit > hwmgr->default_power_limit)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
hwmgr->power_limit = limit;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (limit == NULL)
return -EINVAL;
- hwmgr = pp_handle->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (default_limit)
*limit = hwmgr->default_power_limit;
else
*limit = hwmgr->power_limit;
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_store_dal_configuration_data(hwmgr, display_config);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_display_power_level(void *handle,
struct amd_pp_simple_clock_info *output)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (output == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_dal_power_level(hwmgr, output);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
{
struct amd_pp_simple_clock_info simple_clocks;
struct pp_clock_info hw_clocks;
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
phm_get_dal_power_level(hwmgr, &simple_clocks);
if (ret) {
pr_info("Error in phm_get_clock_info \n");
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return -EINVAL;
}
clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
}
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clocks)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!wm_with_clock_ranges)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
wm_with_clock_ranges);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
if (!clock)
return -EINVAL;
- hwmgr = ((struct pp_instance *)handle)->hwmgr;
-
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
ret = phm_display_clock_voltage_request(hwmgr, clock);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (clocks == NULL)
return -EINVAL;
- mutex_lock(&pp_handle->pp_lock);
+ mutex_lock(&hwmgr->smu_lock);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
ret = phm_get_max_high_clocks(hwmgr, clocks);
- mutex_unlock(&pp_handle->pp_lock);
+ mutex_unlock(&hwmgr->smu_lock);
return ret;
}
static int pp_set_mmhub_powergating_by_smu(void *handle)
{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(pp_handle);
+ ret = pp_check(hwmgr);
if (ret)
return ret;
- hwmgr = pp_handle->hwmgr;
-
if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
}
-const struct amd_pm_funcs pp_dpm_funcs = {
+static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
.force_performance_level = pp_dpm_force_performance_level,
projects / users / hch / xfs.git / commitdiff