arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts

Add a minimal dts for i.MX95 19x19 EVK board:
 - lpuart1 as console
 - sdhc1/2 as storage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index fae82f75c46a26eaf03b9f222381608d4597bd69..42ad3abde4fcdfae3dde15804b98d7fd376ac763 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
 
 imx8mm-venice-gw72xx-0x-imx219-dtbs    := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
 imx8mm-venice-gw72xx-0x-rpidsi-dtbs    := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
new file mode 100644 (file)
index 0000000..675abb7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include "imx95.dtsi"
+
+/ {
+       model = "NXP i.MX95 19X19 board";
+       compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
+
+       aliases {
+               mmc0 = &usdhc1;
+               mmc1 = &usdhc2;
+               serial0 = &lpuart1;
+       };
+
+       chosen {
+               stdout-path = &lpuart1;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0 0x80000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               linux_cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       alloc-ranges = <0 0x80000000 0 0x7f000000>;
+                       size = <0 0x3c000000>;
+                       linux,cma-default;
+                       reusable;
+               };
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2 {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+               regulator-name = "VDD_SD2_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               off-on-delay-us = <12000>;
+       };
+};
+
+&lpuart1 {
+       /* console */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&mu7 {
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       pinctrl-3 = <&pinctrl_usdhc1>;
+       bus-width = <8>;
+       non-removable;
+       no-sdio;
+       no-sd;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&wdog3 {
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&scmi_iomuxc {
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX      0x31e
+                       IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX      0x31e
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       IMX95_PAD_SD1_CLK__USDHC1_CLK                   0x158e
+                       IMX95_PAD_SD1_CMD__USDHC1_CMD                   0x138e
+                       IMX95_PAD_SD1_DATA0__USDHC1_DATA0               0x138e
+                       IMX95_PAD_SD1_DATA1__USDHC1_DATA1               0x138e
+                       IMX95_PAD_SD1_DATA2__USDHC1_DATA2               0x138e
+                       IMX95_PAD_SD1_DATA3__USDHC1_DATA3               0x138e
+                       IMX95_PAD_SD1_DATA4__USDHC1_DATA4               0x138e
+                       IMX95_PAD_SD1_DATA5__USDHC1_DATA5               0x138e
+                       IMX95_PAD_SD1_DATA6__USDHC1_DATA6               0x138e
+                       IMX95_PAD_SD1_DATA7__USDHC1_DATA7               0x138e
+                       IMX95_PAD_SD1_STROBE__USDHC1_STROBE             0x158e
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       IMX95_PAD_SD1_CLK__USDHC1_CLK                   0x158e
+                       IMX95_PAD_SD1_CMD__USDHC1_CMD                   0x138e
+                       IMX95_PAD_SD1_DATA0__USDHC1_DATA0               0x138e
+                       IMX95_PAD_SD1_DATA1__USDHC1_DATA1               0x138e
+                       IMX95_PAD_SD1_DATA2__USDHC1_DATA2               0x138e
+                       IMX95_PAD_SD1_DATA3__USDHC1_DATA3               0x138e
+                       IMX95_PAD_SD1_DATA4__USDHC1_DATA4               0x138e
+                       IMX95_PAD_SD1_DATA5__USDHC1_DATA5               0x138e
+                       IMX95_PAD_SD1_DATA6__USDHC1_DATA6               0x138e
+                       IMX95_PAD_SD1_DATA7__USDHC1_DATA7               0x138e
+                       IMX95_PAD_SD1_STROBE__USDHC1_STROBE             0x158e
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       IMX95_PAD_SD1_CLK__USDHC1_CLK                   0x15fe
+                       IMX95_PAD_SD1_CMD__USDHC1_CMD                   0x13fe
+                       IMX95_PAD_SD1_DATA0__USDHC1_DATA0               0x13fe
+                       IMX95_PAD_SD1_DATA1__USDHC1_DATA1               0x13fe
+                       IMX95_PAD_SD1_DATA2__USDHC1_DATA2               0x13fe
+                       IMX95_PAD_SD1_DATA3__USDHC1_DATA3               0x13fe
+                       IMX95_PAD_SD1_DATA4__USDHC1_DATA4               0x13fe
+                       IMX95_PAD_SD1_DATA5__USDHC1_DATA5               0x13fe
+                       IMX95_PAD_SD1_DATA6__USDHC1_DATA6               0x13fe
+                       IMX95_PAD_SD1_DATA7__USDHC1_DATA7               0x13fe
+                       IMX95_PAD_SD1_STROBE__USDHC1_STROBE             0x15fe
+               >;
+       };
+
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+               fsl,pins = <
+                       IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7            0x31e
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+               fsl,pins = <
+                       IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0               0x31e
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       IMX95_PAD_SD2_CLK__USDHC2_CLK                   0x158e
+                       IMX95_PAD_SD2_CMD__USDHC2_CMD                   0x138e
+                       IMX95_PAD_SD2_DATA0__USDHC2_DATA0               0x138e
+                       IMX95_PAD_SD2_DATA1__USDHC2_DATA1               0x138e
+                       IMX95_PAD_SD2_DATA2__USDHC2_DATA2               0x138e
+                       IMX95_PAD_SD2_DATA3__USDHC2_DATA3               0x138e
+                       IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT           0x51e
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+               fsl,pins = <
+                       IMX95_PAD_SD2_CLK__USDHC2_CLK                   0x158e
+                       IMX95_PAD_SD2_CMD__USDHC2_CMD                   0x138e
+                       IMX95_PAD_SD2_DATA0__USDHC2_DATA0               0x138e
+                       IMX95_PAD_SD2_DATA1__USDHC2_DATA1               0x138e
+                       IMX95_PAD_SD2_DATA2__USDHC2_DATA2               0x138e
+                       IMX95_PAD_SD2_DATA3__USDHC2_DATA3               0x138e
+                       IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT           0x51e
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+               fsl,pins = <
+                       IMX95_PAD_SD2_CLK__USDHC2_CLK                   0x15fe
+                       IMX95_PAD_SD2_CMD__USDHC2_CMD                   0x13fe
+                       IMX95_PAD_SD2_DATA0__USDHC2_DATA0               0x13fe
+                       IMX95_PAD_SD2_DATA1__USDHC2_DATA1               0x13fe
+                       IMX95_PAD_SD2_DATA2__USDHC2_DATA2               0x13fe
+                       IMX95_PAD_SD2_DATA3__USDHC2_DATA3               0x13fe
+                       IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT           0x51e
+               >;
+       };
+};