}
 EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_an_restart);
 
+#define C45_ADDR(d,a)  (MII_ADDR_C45 | (d) << 16 | (a))
+void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
+                                  struct phylink_link_state *state)
+{
+       struct mii_bus *bus = pcs->bus;
+       int addr = pcs->addr;
+       int stat;
+
+       stat = mdiobus_read(bus, addr, C45_ADDR(MDIO_MMD_PCS, MDIO_STAT1));
+       if (stat < 0) {
+               state->link = false;
+               return;
+       }
+
+       state->link = !!(stat & MDIO_STAT1_LSTATUS);
+       if (!state->link)
+               return;
+
+       switch (state->interface) {
+       case PHY_INTERFACE_MODE_10GBASER:
+               state->speed = SPEED_10000;
+               state->duplex = DUPLEX_FULL;
+               break;
+
+       default:
+               break;
+       }
+}
+EXPORT_SYMBOL_GPL(phylink_mii_c45_pcs_get_state);
+
 MODULE_LICENSE("GPL v2");
 
                                        const struct phylink_link_state *state);
 void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
 
+void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
+                                  struct phylink_link_state *state);
 #endif