PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3

The devicetree binding documentation for the Xilinx NWL PCIe root port
bridge shows an example which uses an interrupt-map property to map PCI
INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ
domain with size 4, which therefore covers the hwirq range 0-3.

This means that if we attempt to make use of the INTD interrupt then we're
likely to hit a WARN() in irq_domain_associate() because INTD, or hwirw=4,
is outside of the range covered by the IRQ domain.  irq_domain_associate()
will then return -EINVAL and we'll be unable to make use of INTD.

Fix this by making use of the pci_irqd_intx_xlate() helper function to
translate the 1-4 range used in the DT to a 0-3 range used within the
driver, and stop adding 1 to decoded hwirq numbers.

Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro
& drop the custom INTX definitions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>

diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index eec641a34fc54816684648c7bfa788e75874758f..573847f4b9bceaa3719d5b0b37efb626864ecce3 100644 (file)
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -133,7 +133,6 @@
 #define CFG_DMA_REG_BAR                        GENMASK(2, 0)
 
 #define INT_PCI_MSI_NR                 (2 * 32)
-#define INTX_NUM                       4
 
 /* Readin the PS_LINKUP */
 #define PS_LINKUP_OFFSET               0x00000238
@@ -334,9 +333,8 @@ static void nwl_pcie_leg_handler(struct irq_desc *desc)
 
        while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
                                MSGF_LEG_SR_MASKALL) != 0) {
-               for_each_set_bit(bit, &status, INTX_NUM) {
-                       virq = irq_find_mapping(pcie->legacy_irq_domain,
-                                               bit + 1);
+               for_each_set_bit(bit, &status, PCI_NUM_INTX) {
+                       virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
                        if (virq)
                                generic_handle_irq(virq);
                }
@@ -436,6 +434,7 @@ static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
 
 static const struct irq_domain_ops legacy_domain_ops = {
        .map = nwl_legacy_map,
+       .xlate = pci_irqd_intx_xlate,
 };
 
 #ifdef CONFIG_PCI_MSI
@@ -559,7 +558,7 @@ static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
        }
 
        pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
-                                                       INTX_NUM,
+                                                       PCI_NUM_INTX,
                                                        &legacy_domain_ops,
                                                        pcie);