drm/xe/dg1: Fix power gate sequence.

sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

VLK: 16314, 4304

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241219235536.454270-1-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 2f12e9c029315c1400059b2e7fdf53117c09c3a9)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index fd80afeef56a7c942a725767d391ef713720300c..ffd3ba7f6656160eb02d0b3d98ffc639813ec606 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -122,10 +122,12 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
        if (!xe_gt_is_media_type(gt))
                gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;
 
-       for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
-               if ((gt->info.engine_mask & BIT(i)))
-                       gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
-                                                    VDN_MFXVDENC_POWERGATE_ENABLE(j));
+       if (xe->info.platform != XE_DG1) {
+               for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
+                       if ((gt->info.engine_mask & BIT(i)))
+                               gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
+                                                            VDN_MFXVDENC_POWERGATE_ENABLE(j));
+               }
        }
 
        fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);