{
        int ret = 0;
        u8 status;
-       unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 
        ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
        if (ret < 0) {
                        OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
                        OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
                /*
-                * The RX comes immediately after TX. It
-                * triggers another interrupt before we
-                * sleep. So we have to wait for RXCOMPLETE bit.
+                * The RX comes immediately after TX.
                 */
-               while (!(hdq_data->hdq_irqstatus
-                       & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
-                       && time_before(jiffies, timeout)) {
-                       schedule_timeout_uninterruptible(1);
-               }
+               wait_event_timeout(hdq_wait_queue,
+                                  (hdq_data->hdq_irqstatus
+                                   & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
+                                  OMAP_HDQ_TIMEOUT);
+
                hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
                        OMAP_HDQ_CTRL_STATUS_DIR);
                status = hdq_data->hdq_irqstatus;