drm/amd/pp: Disable OD feature on APU/Iceland

Not supported on APUs or Iceland.
and still not enabled on CI.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 26904462d23a72b8fb77e286319260bdcd20a3dc..33eabc18211dcc2c85e3973db28e42adedad59c3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -167,9 +167,11 @@ int hwmgr_early_init(struct pp_instance *handle)
                hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
                                        PP_ENABLE_GFX_CG_THRU_SMU);
                hwmgr->pp_table_version = PP_TABLE_V0;
+               hwmgr->od_enabled = false;
                smu7_init_function_pointers(hwmgr);
                break;
        case AMDGPU_FAMILY_CZ:
+               hwmgr->od_enabled = false;
                hwmgr->smumgr_funcs = &cz_smu_funcs;
                cz_init_function_pointers(hwmgr);
                break;
@@ -181,6 +183,7 @@ int hwmgr_early_init(struct pp_instance *handle)
                        hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
                                                PP_ENABLE_GFX_CG_THRU_SMU);
                        hwmgr->pp_table_version = PP_TABLE_V0;
+                       hwmgr->od_enabled = false;
                        break;
                case CHIP_TONGA:
                        hwmgr->smumgr_funcs = &tonga_smu_funcs;
@@ -218,6 +221,7 @@ int hwmgr_early_init(struct pp_instance *handle)
        case AMDGPU_FAMILY_RV:
                switch (hwmgr->chip_id) {
                case CHIP_RAVEN:
+                       hwmgr->od_enabled = false;
                        hwmgr->smumgr_funcs = &rv_smu_funcs;
                        rv_init_function_pointers(hwmgr);
                        break;