drm/i915: Drop a few unwanted tabs from skl+ plane reg defines

A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.

v2: Rebase

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513170008.15338-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index e8d399592fd3ce69d1d38e6a91c0efb1ed08c528..0b4f97059479a5c4c16f985d8817009c4ecfcef2 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -205,17 +205,17 @@
 #define _PLANE_CUS_CTL_2(pipe)         _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
 #define PLANE_CUS_CTL(pipe, plane)     _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
 #define   PLANE_CUS_ENABLE                     REG_BIT(31)
-#define   PLANE_CUS_Y_PLANE_MASK                       REG_BIT(30)
+#define   PLANE_CUS_Y_PLANE_MASK               REG_BIT(30)
 #define   PLANE_CUS_Y_PLANE_4_RKL              REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_5_RKL              REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
 #define   PLANE_CUS_Y_PLANE_6_ICL              REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
 #define   PLANE_CUS_Y_PLANE_7_ICL              REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE               REG_BIT(19)
+#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE       REG_BIT(19)
 #define   PLANE_CUS_HPHASE_MASK                        REG_GENMASK(17, 16)
 #define   PLANE_CUS_HPHASE_0                   REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
 #define   PLANE_CUS_HPHASE_0_25                        REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
 #define   PLANE_CUS_HPHASE_0_5                 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE               REG_BIT(15)
+#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE       REG_BIT(15)
 #define   PLANE_CUS_VPHASE_MASK                        REG_GENMASK(13, 12)
 #define   PLANE_CUS_VPHASE_0                   REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
 #define   PLANE_CUS_VPHASE_0_25                        REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)