return err;
 }
 
-static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
+static void clear_irq_vector(int irq, struct irq_cfg *cfg)
 {
        int cpu, vector;
+       unsigned long flags;
 
+       raw_spin_lock_irqsave(&vector_lock, flags);
        BUG_ON(!cfg->vector);
 
        vector = cfg->vector;
        cfg->vector = 0;
        cpumask_clear(cfg->domain);
 
-       if (likely(!cfg->move_in_progress))
+       if (likely(!cfg->move_in_progress)) {
+               raw_spin_unlock_irqrestore(&vector_lock, flags);
                return;
+       }
+
        for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
                for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
                        if (per_cpu(vector_irq, cpu)[vector] != irq)
                }
        }
        cfg->move_in_progress = 0;
+       raw_spin_unlock_irqrestore(&vector_lock, flags);
 }
 
 void __setup_vector_irq(int cpu)
                                         &dest)) {
                pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
                        mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
-               __clear_irq_vector(irq, cfg);
+               clear_irq_vector(irq, cfg);
 
                return;
        }
        if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
                pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
                        mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
-               __clear_irq_vector(irq, cfg);
+               clear_irq_vector(irq, cfg);
 
                return;
        }
 void arch_teardown_hwirq(unsigned int irq)
 {
        struct irq_cfg *cfg = irq_cfg(irq);
-       unsigned long flags;
 
        free_remapped_irq(irq);
-       raw_spin_lock_irqsave(&vector_lock, flags);
-       __clear_irq_vector(irq, cfg);
-       raw_spin_unlock_irqrestore(&vector_lock, flags);
+       clear_irq_vector(irq, cfg);
        free_irq_cfg(irq, cfg);
 }