if (ld_node != &fsl_chan->ld_queue) {
                /* Get the ld start address from ld_queue */
                next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
-               dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
-                               (void *)next_dest_addr);
+               dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
+                               (unsigned long long)next_dest_addr);
                set_cdar(fsl_chan, next_dest_addr);
                dma_start(fsl_chan);
        } else {
         */
        if (stat & FSL_DMA_SR_EOSI) {
                dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
-               dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
-                       (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
+               dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
+                       (unsigned long long)get_cdar(fsl_chan),
+                       (unsigned long long)get_ndar(fsl_chan));
                stat &= ~FSL_DMA_SR_EOSI;
                update_cookie = 1;
        }
        }
 
        dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
-                       "controller at %p...\n",
-                       match->compatible, (void *)fdev->reg.start);
+                       "controller at 0x%llx...\n",
+                       match->compatible, (unsigned long long)fdev->reg.start);
        fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
                                                - fdev->reg.start + 1);