Bug fixes:

  - There was a silly bug in common/cmd_net.c which crippled the
    "rarpboot" and "tftpboot" commands ==> fixed
  - Changed mpc8xx/cpu_init.c again to allow for boot ROMS to be 8,
    16 or 32 bit wide (lost this fix by accident)
  - Allow to set the MF bits using the CFG_PLPRCR definition

diff --git a/common/cmd_net.c b/common/cmd_net.c
index 64cf63c2ee656fdb337f2c1675fb15d0d5b23af3..7def767db9e6d4b367e746161ad46b1a764e128e 100644 (file)
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -57,13 +57,13 @@ netboot_common (int proto, cmd_tbl_t *cmdtp, bd_t *bd, int argc, char *argv[])
        extern ulong TftpLoadAddress;
 
        switch (argc) {
-       case 1: rc = NetLoop(bd, BOOTP, "", -1);
+       case 1: rc = NetLoop(bd, proto, "", -1);
                break;
        case 2: asc_to_hex(argv[1], &addr);
-               rc = NetLoop(bd, BOOTP, "", addr);
+               rc = NetLoop(bd, proto, "", addr);
                break;
        case 3: asc_to_hex(argv[1], &addr);
-               rc = NetLoop(bd, BOOTP, argv[2], addr);
+               rc = NetLoop(bd, proto, argv[2], addr);
                break;
        default: printf ("Usage:\n%s\n", cmdtp->usage);
                return;

diff --git a/mpc8xx/cpu_init.c b/mpc8xx/cpu_init.c
index 757ca9f26fa40d6d45b9b9b69f12d5e729d2b548..860b49641d860dcf52a0e1eb46e621fefd77f8b0 100644 (file)
--- a/mpc8xx/cpu_init.c
+++ b/mpc8xx/cpu_init.c
@@ -61,9 +61,19 @@ cpu_init_f (volatile immap_t *immr)
     /* PLL (CPU clock) settings (15-30) */
 
     immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+
+    /* If CFG_PLPRCR (set in the various *_config.h files) tries to
+     * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
+     * otherwise OR in CFG_PLPRCR so we do not change the currentMF
+     * field value.
+     */
+#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
+    reg = CFG_PLPRCR;                  /* reset control bits   */
+#else
     reg = immr->im_clkrst.car_plprcr;
     reg &= PLPRCR_MF_MSK;              /* isolate MF field     */
     reg |= CFG_PLPRCR;                 /* reset control bits   */
+#endif
     immr->im_clkrst.car_plprcr = reg;
 
     /* System integration timers. Don't change EBDF! (15-27) */
@@ -79,7 +89,7 @@ cpu_init_f (volatile immap_t *immr)
      */
 
     /* perform BR0 reset that MPC850 Rev. A can't guarantee */
-    memctl->memc_br0 = 0x00000001;     /* just "bank valid" bit */
+    memctl->memc_br0 |= 0x00000001;    /* just "bank valid" bit */
 
     /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
      * addresses - these have to be modified later when FLASH size