#define DMA2_EXT_REG           0x4D6
 
 #ifndef __powerpc64__
-    /* in arch/ppc/kernel/setup.c -- Cort */
+    /* in arch/powerpc/kernel/setup_32.c -- Cort */
     extern unsigned int DMA_MODE_WRITE;
     extern unsigned int DMA_MODE_READ;
-    extern unsigned long ISA_DMA_THRESHOLD;
 #else
     #define DMA_MODE_READ      0x44    /* I/O to memory, no autoinit, increment, single mode */
     #define DMA_MODE_WRITE     0x48    /* memory to I/O, no autoinit, increment, single mode */
 
 int smp_hw_index[NR_CPUS];
 EXPORT_SYMBOL(smp_hw_index);
 
-unsigned long ISA_DMA_THRESHOLD;
 unsigned int DMA_MODE_READ;
 unsigned int DMA_MODE_WRITE;
 
 
        if (!of_machine_is_compatible("pika,warp"))
                return 0;
 
-       /* For arch_dma_alloc */
-       ISA_DMA_THRESHOLD = ~0L;
-
        return 1;
 }
 
 
        if (strcmp(model, "EFIKA5K2"))
                return 0;
 
-       ISA_DMA_THRESHOLD = ~0L;
        DMA_MODE_READ = 0x44;
        DMA_MODE_WRITE = 0x48;
 
 
                 */
                cur_cpu_spec->cpu_features &= ~CPU_FTR_NEED_COHERENT;
 
-               ISA_DMA_THRESHOLD = 0x00ffffff;
                DMA_MODE_READ = 0x44;
                DMA_MODE_WRITE = 0x48;
 
 
        if (strcmp(dtype, "chrp"))
                return 0;
 
-       ISA_DMA_THRESHOLD = ~0L;
        DMA_MODE_READ = 0x44;
        DMA_MODE_WRITE = 0x48;
 
 
 
 #ifdef CONFIG_PPC32
        /* isa_io_base gets set in pmac_pci_init */
-       ISA_DMA_THRESHOLD = ~0L;
        DMA_MODE_READ = 1;
        DMA_MODE_WRITE = 2;
 #endif /* CONFIG_PPC32 */