s390/entry: avoid setting up backchain in ext|io handlers

Currently when interrupt arrives to cpu while in kernel context
INT_HANDLER macro (used for ext_int_handler and io_int_handler)
allocates new stack frame and pt_regs on the kernel stack and
sets up the backchain to jump over the pt_regs to the frame which has
been interrupted. This is not ideal to two reasons:

1. This hides the fact that kernel stack contains interrupt frame in it
   and hence breaks arch_stack_walk_reliable(), which needs to know that to
   guarantee "reliability" and checks that there are no pt_regs on the way.

2. It breaks the backchain unwinder logic, which assumes that the next
   stack frame after an interrupt frame is reliable, while it is not.
   In some cases (when r14 contains garbage) this leads to early unwinding
   termination with an error, instead of marking frame as unreliable
   and continuing.

To address that, only set backchain to 0.

Fixes: 56e62a737028 ("s390: convert to generic entry")
Reviewed-by: Sven Schnelle <svens@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>

diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index c10b9f31eef7993fde313814cb3d3b68db724a90..235bf2ac335976e5672647bf32499f626bf9a5c5 100644 (file)
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -401,15 +401,13 @@ ENTRY(\name)
        brasl   %r14,.Lcleanup_sie_int
 #endif
 0:     CHECK_STACK __LC_SAVE_AREA_ASYNC
-       lgr     %r11,%r15
        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
-       stg     %r11,__SF_BACKCHAIN(%r15)
        j       2f
 1:     BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
        lctlg   %c1,%c1,__LC_KERNEL_ASCE
        lg      %r15,__LC_KERNEL_STACK
-       xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
-2:     la      %r11,STACK_FRAME_OVERHEAD(%r15)
+2:     xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+       la      %r11,STACK_FRAME_OVERHEAD(%r15)
        stmg    %r0,%r7,__PT_R0(%r11)
        # clear user controlled registers to prevent speculative use
        xgr     %r0,%r0