drm/amd/display: Add some missing register definitions

[Why&How]
Add some missing register definitions and rearrange some others to
maintain consistency with related definitions.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index a3fee929cd120f5e414e3f158ea74ad853df35e5..86233f94db4ae38414b165a354e7288a9978928b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -98,6 +98,29 @@
        SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
        SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
 
+#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
+       SRII(PIXEL_RATE_CNTL, blk, 0), \
+       SRII(PIXEL_RATE_CNTL, blk, 1),\
+       SRII(PIXEL_RATE_CNTL, blk, 2),\
+       SRII(PIXEL_RATE_CNTL, blk, 3), \
+       SRII(PIXEL_RATE_CNTL, blk, 4)
+
+#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
+
+#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
+       SRII(PIXEL_RATE_CNTL, blk, 0), \
+       SRII(PIXEL_RATE_CNTL, blk, 1)
+
+#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
+
+
 #define HWSEQ_PHYPLL_REG_LIST_201(blk) \
        SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
        SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
@@ -387,7 +410,11 @@
        SR(MPC_CRC_RESULT_C), \
        SR(MPC_CRC_RESULT_AR), \
        SR(AZALIA_AUDIO_DTO), \
-       SR(AZALIA_CONTROLLER_CLOCK_GATING)
+       SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+       SR(HPO_TOP_CLOCK_CONTROL), \
+       SR(ODM_MEM_PWR_CTRL3), \
+       SR(DMU_MEM_PWR_CNTL), \
+       SR(MMHUBBUB_MEM_PWR_CNTL)
 
 #define HWSEQ_DCN301_REG_LIST()\
        SR(REFCLK_CNTL), \
@@ -508,8 +535,11 @@
        SR(D5VGA_CONTROL), \
        SR(D6VGA_CONTROL), \
        SR(DC_IP_REQUEST_CNTL), \
+       HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
+       HWSEQ_PHYPLL_REG_LIST_302(OTG), \
        SR(AZALIA_AUDIO_DTO), \
-       SR(AZALIA_CONTROLLER_CLOCK_GATING)
+       SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+       SR(HPO_TOP_CLOCK_CONTROL)
 
 #define HWSEQ_DCN303_REG_LIST() \
        HWSEQ_DCN_REG_LIST(), \
@@ -540,28 +570,6 @@
        SR(AZALIA_CONTROLLER_CLOCK_GATING), \
        SR(HPO_TOP_CLOCK_CONTROL)
 
-#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
-       SRII(PIXEL_RATE_CNTL, blk, 0), \
-       SRII(PIXEL_RATE_CNTL, blk, 1),\
-       SRII(PIXEL_RATE_CNTL, blk, 2),\
-       SRII(PIXEL_RATE_CNTL, blk, 3), \
-       SRII(PIXEL_RATE_CNTL, blk, 4)
-
-#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
-
-#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
-       SRII(PIXEL_RATE_CNTL, blk, 0), \
-       SRII(PIXEL_RATE_CNTL, blk, 1)
-
-#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
-       SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
-
 struct dce_hwseq_registers {
        uint32_t DCFE_CLOCK_CONTROL[6];
        uint32_t DCFEV_CLOCK_CONTROL;
@@ -663,14 +671,15 @@ struct dce_hwseq_registers {
        uint32_t MC_VM_XGMI_LFB_CNTL;
        uint32_t AZALIA_AUDIO_DTO;
        uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+       /* MMHUB VM */
+       uint32_t MC_VM_FB_LOCATION_BASE;
+       uint32_t MC_VM_FB_LOCATION_TOP;
+       uint32_t MC_VM_FB_OFFSET;
+       uint32_t MMHUBBUB_MEM_PWR_CNTL;
        uint32_t HPO_TOP_CLOCK_CONTROL;
        uint32_t ODM_MEM_PWR_CTRL3;
        uint32_t DMU_MEM_PWR_CNTL;
-       uint32_t MMHUBBUB_MEM_PWR_CNTL;
        uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
-       uint32_t MC_VM_FB_LOCATION_BASE;
-       uint32_t MC_VM_FB_LOCATION_TOP;
-       uint32_t MC_VM_FB_OFFSET;
        uint32_t HPO_TOP_HW_CONTROL;
 };
  /* set field name */
@@ -915,6 +924,7 @@ struct dce_hwseq_registers {
 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
        HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
        HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+       HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh), \
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
        HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
@@ -1012,7 +1022,8 @@ struct dce_hwseq_registers {
        HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
        HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
        HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
-       HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+       HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+       HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh)
 
 #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \
        HWSEQ_DCN_MASK_SH_LIST(mask_sh), \

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
index 537aee0536d3cb4afa850f245ace9cb23f5fa5aa..f2f8f9b39c6b4a3ca1548d330d3c11069add0809 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
@@ -15805,6 +15805,11 @@
 #define mmDME6_DME_MEMORY_CONTROL                                                                      0x093d
 #define mmDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             3
 
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x0
+#define mmHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+
 // base address: 0x1a698
 #define mmDC_PERFMON29_PERFCOUNTER_CNTL                                                                0x0e66
 #define mmDC_PERFMON29_PERFCOUNTER_CNTL_BASE_IDX                                                       3

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
index f9d90b0985196032d42770f8b78c6bb2e9a2c649..e0a447351623bfa2df5a7e7429e1479826bc9a7a 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
@@ -60666,7 +60666,12 @@
 #define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
 #define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
 
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT                                              0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK                                                0x00000200L
 
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
 //DC_PERFMON29_PERFCOUNTER_CNTL
 #define DC_PERFMON29_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
 #define DC_PERFMON29_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
index 476469d41d730dd7a9f4a95613aeaff6658c07eb..b45a35aae24146085a4e1f1315d865cd5d6c99a2 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
@@ -14205,6 +14205,10 @@
 
 
 
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x0
+#define mmHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
 
 // base address: 0x1a698
 #define mmDC_PERFMON26_PERFCOUNTER_CNTL                                                                0x0e66

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
index b9de0ebc8b03526850d761d6a66f59586d2e9de5..3dae29f9581e08c9a029a9816213799f6a20f448 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
@@ -52401,7 +52401,10 @@
 #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
 #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
 
-
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT                                              0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK                                                0x00000200L
 
 // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
 //DC_PERFMON26_PERFCOUNTER_CNTL