* of the MIPS kernel code does not use the percpu IRQ API for
         * the CP0 timer and performance counter interrupts.
         */
-       if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) {
+       switch (intr) {
+       case GIC_LOCAL_INT_TIMER:
+       case GIC_LOCAL_INT_PERFCTR:
+       case GIC_LOCAL_INT_FDC:
+               irq_set_chip_and_handler(virq,
+                                        &gic_all_vpes_local_irq_controller,
+                                        handle_percpu_irq);
+               break;
+       default:
                irq_set_chip_and_handler(virq,
                                         &gic_local_irq_controller,
                                         handle_percpu_devid_irq);
                irq_set_percpu_devid(virq);
-       } else {
-               irq_set_chip_and_handler(virq,
-                                        &gic_all_vpes_local_irq_controller,
-                                        handle_percpu_irq);
+               break;
        }
 
        spin_lock_irqsave(&gic_lock, flags);