drm/amdgpu: initialize GC IP v11.5.2

Initialize GC 11.5.2 and set gfx hw configuration.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0d078d0db162b65fec7f43193bb87014b1c1a191..9acdabd7719a1ebf6479208bdfd87d3179685218 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1054,6 +1054,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
        case IP_VERSION(11, 0, 4):
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
+       case IP_VERSION(11, 5, 2):
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1534,6 +1535,7 @@ static int gfx_v11_0_sw_init(void *handle)
        case IP_VERSION(11, 0, 4):
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
+       case IP_VERSION(11, 5, 2):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
@@ -2782,7 +2784,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
                    amdgpu_ip_version(adev, GC_HWIP, 0) ==
                            IP_VERSION(11, 0, 4) ||
                    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||
-                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1))
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||
+                   amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2))
                        bootload_status = RREG32_SOC15(GC, 0,
                                        regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
                else
@@ -5296,6 +5299,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
                case IP_VERSION(11, 0, 4):
                case IP_VERSION(11, 5, 0):
                case IP_VERSION(11, 5, 1):
+               case IP_VERSION(11, 5, 2):
                        WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
                        break;
                default:
@@ -5332,6 +5336,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
        case IP_VERSION(11, 0, 4):
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
+       case IP_VERSION(11, 5, 2):
                if (!enable)
                        amdgpu_gfx_off_ctrl(adev, false);
 
@@ -5364,6 +5369,7 @@ static int gfx_v11_0_set_clockgating_state(void *handle,
        case IP_VERSION(11, 0, 4):
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
+       case IP_VERSION(11, 5, 2):
                gfx_v11_0_update_gfx_clock_gating(adev,
                                state ==  AMD_CG_STATE_GATE);
                break;