x86/speculation/mds: Add basic bug infrastructure for MDS

commit ed5194c2732c8084af9fd159c146ea92bf137128 upstream

Microarchitectural Data Sampling (MDS), is a class of side channel attacks
on internal buffers in Intel CPUs. The variants are:

 - Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)
 - Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)
 - Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)

MSBDS leaks Store Buffer Entries which can be speculatively forwarded to a
dependent load (store-to-load forwarding) as an optimization. The forward
can also happen to a faulting or assisting load operation for a different
memory address, which can be exploited under certain conditions. Store
buffers are partitioned between Hyper-Threads so cross thread forwarding is
not possible. But if a thread enters or exits a sleep state the store
buffer is repartitioned which can expose data from one thread to the other.

MFBDS leaks Fill Buffer Entries. Fill buffers are used internally to manage
L1 miss situations and to hold data which is returned or sent in response
to a memory or I/O operation. Fill buffers can forward data to a load
operation and also write data to the cache. When the fill buffer is
deallocated it can retain the stale data of the preceding operations which
can then be forwarded to a faulting or assisting load operation, which can
be exploited under certain conditions. Fill buffers are shared between
Hyper-Threads so cross thread leakage is possible.

MLDPS leaks Load Port Data. Load ports are used to perform load operations
from memory or I/O. The received data is then forwarded to the register
file or a subsequent operation. In some implementations the Load Port can
contain stale data from a previous operation which can be forwarded to
faulting or assisting loads under certain conditions, which again can be
exploited eventually. Load ports are shared between Hyper-Threads so cross
thread leakage is possible.

All variants have the same mitigation for single CPU thread case (SMT off),
so the kernel can treat them as one MDS issue.

Add the basic infrastructure to detect if the current CPU is affected by
MDS.

[ tglx: Rewrote changelog ]

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 928a58d368271748e2d8a4bdb7ba1412c5f1348f)

Orabug: 29526900
CVE: CVE-2018-12126
CVE: CVE-2018-12130
CVE: CVE-2018-12127

Signed-off-by: Kanth Ghatraju <kanth.ghatraju@oracle.com>
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 403322a3ce0b781f7063475c2f0487062d2541b4..ab840c00635523bc41f091cb77264d9a9d210e79 100644 (file)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -73,6 +73,7 @@
  */
 #define X86_FEATURE_L1TF_PTEINV                ( 2*32+0) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_FLUSH_L1D          ( 2*32+1) /* Flush L1D cache */
+#define X86_FEATURE_MD_CLEAR           ( 2*32+2) /* VERW clears CPU buffers */
 
 /* Other features, Linux-defined mapping, word 3 */
 /* This range is used for feature bits which conflict or are synthesized */
@@ -297,6 +298,7 @@
 #define X86_BUG_SPECTRE_V2     X86_BUG(16) /* indirect branches */
 #define X86_BUG_SPEC_STORE_BYPASS      X86_BUG(17) /* CPU is affected by speculative store bypass attack */
 #define X86_BUG_L1TF                   X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
+#define X86_BUG_MDS                    X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 9b86df5fe3fb46f31809c4f0a2edd88d5d654af9..6d9f6f98b209ccbe44f0f089c45c55e5ee4923b7 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -68,6 +68,11 @@
                                                 * attack, so no Speculative Store Bypass
                                                 * control required.
                                                 */
+#define ARCH_CAP_MDS_NO                        BIT(5)   /*
+                                                 * Not susceptible to
+                                                 * Microarchitectural Data
+                                                 * Sampling (MDS) vulnerabilities.
+                                                 */
 
 #define MSR_IA32_FLUSH_CMD             0x0000010b
 #define L1D_FLUSH                      BIT(0)  /*

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d75be692724004e71574b8ba189af0404ea42fcb..ef0ef7960c0b5b1eb9e73572cbaa0203b1768a9e 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -805,6 +805,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 #define NO_MELTDOWN    BIT(1)
 #define NO_SSB         BIT(2)
 #define NO_L1TF                BIT(3)
+#define NO_MDS         BIT(4)
 
 #define VULNWL(_vendor, _family, _model, _whitelist)   \
        { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
@@ -821,6 +822,7 @@ static const struct x86_cpu_id cpu_vuln_whitelist[] = {
        VULNWL(INTEL,   5, X86_MODEL_ANY,       NO_SPECULATION),
        VULNWL(NSC,     5, X86_MODEL_ANY,       NO_SPECULATION),
 
+       /* Intel Family 6 */
        VULNWL_INTEL(ATOM_CEDARVIEW,            NO_SPECULATION),
        VULNWL_INTEL(ATOM_CLOVERVIEW,           NO_SPECULATION),
        VULNWL_INTEL(ATOM_PENWELL,              NO_SPECULATION),
@@ -829,7 +831,7 @@ static const struct x86_cpu_id cpu_vuln_whitelist[] = {
 
        VULNWL_INTEL(ATOM_SILVERMONT1,          NO_SSB | NO_L1TF),
        VULNWL_INTEL(ATOM_SILVERMONT2,          NO_SSB | NO_L1TF),
-       VULNWL_INTEL(ATOM_MERRIFIELD,   NO_SSB | NO_L1TF),
+       VULNWL_INTEL(ATOM_MERRIFIELD,           NO_SSB | NO_L1TF),
        VULNWL_INTEL(ATOM_AIRMONT,              NO_SSB | NO_L1TF),
        VULNWL_INTEL(XEON_PHI_KNL,              NO_SSB | NO_L1TF),
        VULNWL_INTEL(XEON_PHI_KNM,              NO_SSB | NO_L1TF),
@@ -837,17 +839,18 @@ static const struct x86_cpu_id cpu_vuln_whitelist[] = {
        VULNWL_INTEL(CORE_YONAH,                NO_SSB),
 
        VULNWL_INTEL(ATOM_MOOREFIELD,           NO_L1TF),
-       VULNWL_INTEL(ATOM_GOLDMONT,             NO_L1TF),
-       VULNWL_INTEL(ATOM_DENVERTON,            NO_L1TF),
-       VULNWL_INTEL(ATOM_GEMINI_LAKE,          NO_L1TF),
 
-       VULNWL_AMD(0x0f,                NO_MELTDOWN | NO_SSB | NO_L1TF),
-       VULNWL_AMD(0x10,                NO_MELTDOWN | NO_SSB | NO_L1TF),
-       VULNWL_AMD(0x11,                NO_MELTDOWN | NO_SSB | NO_L1TF),
-       VULNWL_AMD(0x12,                NO_MELTDOWN | NO_SSB | NO_L1TF),
+       VULNWL_INTEL(ATOM_GOLDMONT,             NO_MDS | NO_L1TF),
+       VULNWL_INTEL(ATOM_DENVERTON,            NO_MDS | NO_L1TF),
+       VULNWL_INTEL(ATOM_GEMINI_LAKE,          NO_MDS | NO_L1TF),
+
+       VULNWL_AMD(0x0f,                NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+       VULNWL_AMD(0x10,                NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+       VULNWL_AMD(0x11,                NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+       VULNWL_AMD(0x12,                NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
 
        /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
-       VULNWL_AMD(X86_FAMILY_ANY,      NO_MELTDOWN | NO_L1TF),
+       VULNWL_AMD(X86_FAMILY_ANY,      NO_MELTDOWN | NO_L1TF | NO_MDS),
        {}
 };
 
@@ -874,6 +877,9 @@ void cpu_set_bug_bits(struct cpuinfo_x86 *c)
        if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO))
                setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
+       if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO))
+               setup_force_cpu_bug(X86_BUG_MDS);
+
        if (cpu_matches(NO_MELTDOWN))
                return;
 

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index de9707071ed4ad9798ffaf866cb495be817f642d..69a47ec0827652a1ca3aa0f88b239bc67e5ae609 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -110,6 +110,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c,
                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
                { X86_FEATURE_INTEL_PT,         CR_EBX,25, 0x00000007, 0 },
+               { X86_FEATURE_MD_CLEAR,         CR_EDX,10, 0x00000007, 0 },
                { X86_FEATURE_IBRS,             CR_EDX,26, 0x00000007, 0 },
                { X86_FEATURE_STIBP,            CR_EDX,27, 0x00000007, 0 },
                { X86_FEATURE_IA32_ARCH_CAPS,   CR_EDX,29, 0x00000007, 0 },